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US 6,645,840 B2Granted
Multi-layered polysilicon process
AssigneeTexas Instruments Incorporated
InventorsDouglas T. Grider, Che Jen Hu
Life of this patent
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Abstract
A method for forming a notched MOS gate structure is described. A multi-layer gate structure is formed (150) where the top layer (140) oxidizes at a faster rate compared to the bottom layer (130). This results in the formation of a notch (165) in the gate structure after thermal oxidation processes.
Claims11
A method of fabricating a transistor gate comprising:
- providing a semiconductor substrate with a gate dielectric;
- forming a first layer over said gate dielectric with a first oxidation rate;
- forming a second layer over said first layer with a second oxidation rate such that said second oxidation rate is less that said first oxidation rate;
- forming a transistor gate structure by etching said first and second layers;
- and
- oxidizing said first and second layers to form a notch mainly in said first layer.
3 more elements
A method of fabricating a transistor gate comprising:
- providing a semiconductor substrate with a gate dielectric;
- forming a first silicon containing layer over said gate dielectric with a first oxidation rate;
- forming a second silicon containing layer over said first layer with a second oxidation rate such that said second oxidation rate is less that said first oxidation rate;
- forming a transistor gate structure by etching said first and second layers;
- and
- oxidizing said first and second silicon containing layers to form a notch mainly in said first layer.
3 more elements
Dependencies are inferred from the claim text.