Etch stop layer for silicon (Si) via etch in three-dimensional (3-D) wafer-to-wafer vertical stack
AssigneeIntel Corporation
InventorsSarah E. Kim, R. Scott List, Tom Letson
Life of this patent
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Abstract
A method of forming a silicon (Si) via in vertically stacked wafers is provided with a contact plug extending from selected metallic lines of a top wafer and an etch stop layer formed prior to the contact plug. Such a method comprises selectively etching through the silicon (Si) of the top wafer until stopped by the etch stop layer to form the Si via; depositing an oxide layer to insulate a sidewall of the Si via; forming a barrier layer on the oxide layer and on the bottom of the Si via; and depositing a conduction metal into the Si via to provide electrical connection between active IC devices located on vertically stacked wafers and an external interconnect.
Claims20
A method of forming a silicon (Si) via in vertically stacked wafers having a contact plug extending from selected metallic lines of a top wafer and an etch stop layer processed before the contact plug, comprising:
- selectively etching through a silicon (Si) of the top wafer until stopped by the etch stop layer comprised of nickel silicide (NiSi) to form a Si via;
- depositing an oxide layer to insulate a sidewall of the Si via;
- forming a barrier layer on the Si via;
- and
- filling the Si via with a conduction metal to provide electrical connection between active IC devices located on vertically stacked wafers and an external interconnect.
A method of forming vertically stacked wafers, comprising:
- forming an etch stop layer comprised of nickel silicide (NiSi) on designated areas on a surface of a top wafer;
- forming a contact plug layer on the etch stop layer on the designated areas on the surface of the top wafer;
- forming vertically stacked wafers by bonding the top wafer with a bottom wafer, via respective metallic lines;
- and
- forming an interwafer via on the top wafer by selectively etching through the silicon (Si) of the top wafer until stopped by the etch stop layer comprised of nickel silicide (NiSi), depositing an oxide layer to insulate a sidewall of the interwafer via, depositing a barrier layer on the oxide layer and on the bottom of the interwafer via, and filling the interwafer via with a conduction metal to provide electrical connection between active IC devices located on vertically stacked wafers and an external.
A method for forming a three-dimensional (3-D) vertically stacked wafer structure, comprising:
- forming a first wafer including an active layer to support one or more integrated circuit (IC) devices;
- forming a second wafer including an active layer to support one or more integrated circuit (IC) devices;
- depositing metallic lines on opposing surfaces of the first and second wafers at designated areas to establish metal bonding between the first and second wafers in a stack and electrical connections between active IC devices on the first and second wafers in the stack;
- and
- forming one or more interwafer vias within the first wafer, to provide electrical connections between active IC devices on the first and second wafers in the stack and an external interconnect,
- wherein each of the interwafer vias is formed by:
- selectively etching through the top wafer until stopped by an etch stop layer comprised of nickel silicide (NiSi);
- depositing the oxide layer to insulate a sidewall of the interwafer via;
- depositing a barrier layer on the oxide layer and on the bottom of the interwafer via;
- and
- filling the interwafer via with the conduction metal to provide electrical connections between active IC devices on the first and second wafers in the stack and the external interconnect.
A method of forming an interwafer via in a three-dimensional (3-D) vertically stacked wafer structure having vertically stacked wafers, comprising:
- selectively etching through a top wafer until stopped by an etch stop layer comprised of nickel silicide (NiSi) to form an interwafer via;
- depositing an oxide layer to insulate a sidewall of the interwafer via;
- depositing a barrier layer on the oxide layer and on the bottom of the interwafer via;
- and
- filling the interwafer via with the conduction metal to provide electrical connections between active IC devices on the vertically stacked wafers and an external interconnect.
Dependencies are inferred from the claim text.