Silicon wafer with embedded optoelectronic material for monolithic OEIC
AssigneeAmberWave Systems Corporation
InventorEugene A. Fitzergald
Life of this patent
Estimating the term…
Abstract
A structure and method of fabricating an optically active layer embedded in a Si wafer, such that the outermost epitaxial layer exposed to the CMOS processing equipment is always Si or another CMOS-compatible material such as SiO2. Since the optoelectronic layer is completely surrounded by Si, the wafer is fully compatible with standard Si CMOS manufacturing. For wavelengths of light longer than the bandgap of Si (1.1 μm), Si is completely transparent and therefore optical signals can be transmitted between the embedded optoelectronic layer and an external waveguide using either normal incidence (through the Si substrate or top Si cap layer) or in-plane incidence (edge coupling).
Claims27
A method of fabricating a semiconductor heterostructure comprising:
- providing an optically active semiconductor material on a Si substrate, said optically active semiconductor material being lattice mismatched with respect to said Si substrate and substantially relaxed, and
- providing a cap layer on said optically active semiconductor material, said cap layer comprising a relaxed SiGe layer with a strained Si cap layer.
A method of fabricating a semiconductor heterostructure comprising:
- providing an optically active semiconductor material on a Si substrate, said optically active semiconductor material being lattice mismatched with respect to said Si substrate and substantially relaxed;
- providing a relaxed, graded Si1-xGex layer graded from x=0 to x≦1, positioned between said Si substrate and said optically active semiconductor material;
- providing a relaxed, graded InxGa1-xAs layer graded from x=0 to x≦1, positioned between said relaxed, graded Si1-xGex layer and said optically active semiconductor material;
- and
- providing a cap layer on said optically active semiconductor material, said cap layer comprising Si.
A method of fabricating a semiconductor heterostructure comprising:
- providing an optically active semiconductor material on a Si substrate, said optically active semiconductor material being lattice mismatched with respect to said Si substrate and substantially relaxed;
- providing a cap layer on said optically active semiconductor material, said cap layer comprising Si;
- and
- providing an insulating layer on said optically active semiconductor material, said cap layer being positioned on said insulating layer.
A method of fabricating a semiconductor heterostructure comprising:
- providing an optically active semiconductor material on a Si substrate, said optically active semiconductor material being lattice mismatched with respect to said Si substrate and substantially relaxed;
- providing a cap layer on said optically active semiconductor material, said cap layer comprising Si;
- providing a first insulating layer on said Si substrate, said optically active semiconductor material being positioned on said first insulating layer;
- and
- providing a second insulating layer on said optically active semiconductor material, said cap layer being positioned on said second insulating layer.
A method of fabricating a semiconductor heterostructure comprising:
- providing an optically active semiconductor material on a Si substrate, said optically active semiconductor material being lattice mismatched with respect to said Si substrate and substantially relaxed;
- providing a cap layer on said optically active semiconductor material, said cap layer comprising Si;
- providing a first insulating layer on said substrate;
- providing a first Si layer on said first insulating layer, said optically active semiconductor material being positioned on said first Si layer;
- providing a second Si layer on said optically active semiconductor material;
- and
- providing a second insulating layer on said second Si layer, said cap layer being positioned on said second insulating layer.
Dependencies are inferred from the claim text.