Methods of forming DRAMS, methods of forming access transistors for DRAM devices, and methods of forming transistor source/drain regions

A method of forming an access transistor construction for a DRAM device, comprising:

• providing a substrate;
• forming an access transistor gate structure over the substrate;
• forming a pair of source/drain regions within the substrate and gatedly connected to one another through the access transistor gate structure;
• forming a halo region within one of the source/drain regions and not forming any halo region within the other of the source/drain regions;
• and
• wherein:
• the source/drain regions comprise lightly n-type doped regions;
• the halo region is a p-type doped region;
• and
• the halo region is formed before the lightly n-type doped regions are formed.

A method of forming an access transistor construction for a DRAM device, comprising:

• providing a substrate;
• forming an access transistor gate structure over the substrate;
• forming a pair of source/drain regions within the substrate and gatedly connected to one another through the access transistor gate structure;
• forming a halo region within one of the source/drain regions and not forming any halo region within the other of the source/drain regions;
• and
• wherein:
• the source/drain regions comprise lightly n-type doped regions;
• by the halo region is a p-type doped region;
• and
• the lightly n-type doped regions are formed with a first implant and a second implant, the first implant occurring before forming the halo region and the second implant occurring after forming the halo region.

A method of forming a DRAM device, comprising:

• providing a substrate having an active area defined therein;
• providing a pair of transistor gate structures over the active area of the substrate, the transistor gate structures being spaced from one another by a gap;
• the active area comprising a first portion covered by the transistor gate structures, a second portion between the transistor gate structures, and a third portion which is neither between the transistor gate structures or covered by the transistor gate structures;
• forming a mask over the third portion of the substrate while leaving the second portion uncovered;
• while the mask is over the third portion of the substrate, first implanting a first dopant into the uncovered second portion, the first implanting comprising implanting the first dopant at a first angle to reach through the gap and to the substrate;
• while the mask is over the third portion of the substrate, second implanting a second dopant into the uncovered second portion, the second implanting comprising implanting the second dopant at a second angle to reach through the gap and to the substrate;
• one of the first and second dopants being an n-type dopant and the other being a p-type dopant;
• and
• forming a pair of capacitor structures and a bitline;
• the bitline being gatedly connected to one of the capacitor structures through one of the transistor gate structures, and being gatedly connected to the other of the capacitor structures through the other of the transistor gate structures.

A method of forming a DRAM device, comprising:

• providing a substrate having an active area defined therein;
• providing a pair of transistor gate structures over the active area of the substrate, the transistor gate structures being spaced from one another by a gap;
• the active area comprising a first portion covered by the transistor gate structures, a second portion between the transistor gate structures, and a third portion which is neither between the transistor gate structures or covered by the transistor gate structures;
• forming a mask over the third portion of the substrate while leaving the second portion uncovered;
• while the mask is over the third portion of the substrate, first implanting a first dopant into the uncovered second portion, the first implanting comprising implanting the first dopant at a first angle to reach through the gap and to the substrate;
• while the mask is over the third portion of the substrate, second implanting a second dopant into the uncovered second portion, the second implanting comprising implanting the second dopant at a second angle to reach through the gap and to the substrate;
• while the mask is over the third portion of the substrate, third implanting a third dopant, the third implanting comprising implanting the third dopant at a third angle to not reach through the gap and to the substrate;
• one of the first and second dopants being an n-type dopant and the other being a p-type dopant;
• the third dopant being p-type dopant;
• and
• forming a pair of capacitor structures and a bitline;
• the bitline being gatedly connected to one of the capacitor structures through one of the transistor gate structures, and being gatedly connected to the other of the capacitor structures through the other of the transistor gate structures.

A method of forming a DRAM device, comprising:

• providing a substrate having a pair of transistor gate structures thereover, the transistor gate structures being spaced from one another by a gap;
• the transistor gate structures having inner sidewalls proximate the gap and inner corners where the inner sidewalls join the substrate;
• the transistor gate structures having outer sidewalls in opposing relation to the inner sidewalls, an inner source/drain region location being defined between the inner sidewalls, and a pair of outer source/drain region locations being defined outwardly proximate the outer sidewalls;
• forming a mask over a portion of the substrate to cover the portion while leaving another portion of the substrate uncovered, the uncovered portion including the gap between the transistor gate structures and the covered portion including the outer source/drain region locations, the mask defining an opening over the gap;
• the mask having a top edge which defines an upper periphery of the opening;
• a threshold angle being defined between a vertical projection and another projection extending from the top edge to an inner corner of one of the transistor gate structures;
• while the mask is over the portion of the substrate, first implanting dopant into the opening in the mask, the first implanting comprising implanting a first dopant at an angle less than the threshold angle to reach through the gap and to the substrate;
• forming outer source/drain regions in the outer source/drain region locations, and forming a shared source/drain region in the inner source/drain region location;
• forming a bitline in electrical contact with the shared source/drain region;
• and
• forming capacitor structures in electrical contact with the outer source/drain regions.

A method of forming transistor source/drain regions, comprising:

• providing a semiconductive material substrate and defining at least two transistor source/drain regions within the substrate, one of the at least two source/drain regions being a first source/drain region and another of the at least two source/drain regions being a second source/drain region;
• forming a masking material over the substrate, the masking material covering some portions of the substrate and having openings extending therethrough to the first and second source/drain regions;
• the opening extending to the first source/drain region having a threshold angle such that dopant implanted at an angle greater than the threshold angle will not reach the substrate of the first source/drain region;
• and
• implanting a dopant into the second source drain region at an angle greater than the threshold angle while the masking material is over the substrate and blocks the dopant from reaching the region.