Metal gate engineering for surface p-channel devices
AssigneeMicron Technology, Inc.
InventorYongjun Jeff Hu
Life of this patent
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Abstract
A semiconductor device, such as a CMOS device, having gates with a high work function in PMOS regions and low work functions in NMOS regions and a method of producing the same. Using nitrogen implantation or plasma annealing, a low work function W (or CoSix)/TaSixNy/GOx/Si gate stack is formed in the NMOS regions while a high work function W (or CoSix)/Ta5Si3/GOx/Si gate stack is formed in the PMOS regions. The improved process also eliminates the need for a nitrided GOx which is known to degrade gm (transconductance) performance. The materials of the semiconductor devices exhibit improved adhesion characteristics to adjacent materials and low internal stress.
Claims13
A method of selectively setting the work functions of semiconductor materials comprising:
- forming a dielectric layer on a semiconductive substrate;
- forming an interconnecting layer atop the dielectric layer wherein the interconnecting layer comprises a metal suicide wherein the metal is matched with the silicide in a stable phase such that the metal is inhibited from reacting with the dielectric layer;
- selectively masking portions of the interconnecting layer;
- and
- reacting unmasked regions of the interconnecting layer with nitrogen so as to transform the unmasked regions of the interconnecting layer to reacted metal-silicon nitride such that the masked regions of the interconnecting layer remain unreacted metal silicide wherein the metal is selected such that the metal-silicon nitride has a lower work function than the unreacted metal silicide.
A method of establishing differential work functions in gate stacks overlying complementary doped regions of semiconductor devices comprising:
- forming a dielectric layer on a semiconductive substrate having complementary regions doped n- and p-type;
- forming an interconnecting layer adjacent the dielectric layer wherein the interconnecting layer comprises a metal silicide wherein the metal is matched with the suicide in a stable phase such that the metal is inhibited from reacting with the dielectric layer;
- selectively masking portions of the interconnecting layer;
- reacting unmasked regions of the interconnecting layer so as to lower the work function of the unmasked regions such that the masked regions of the interconnecting layer remain unreacted;
- and
- selectively removing the masking and portions of the interconnecting layer and the dielectric layer so as to form the gate stacks.
Dependencies are inferred from the claim text.