Polysilicon doped transistor using silicon-on-insulator and double silicon-on-insulator

Abstract

Steep concentration gradients are achieved in semiconductor device of small sizes formed on SOI or double SOI wafers by using implanted polycrystalline material such as polysilicon as a solid diffusion source. Rapid diffusion of impurities along grain boundaries relative to diffusion rates in monocrystalline materials provides a substantially constant impurity concentration at the interface between polycrystalline material and monocrystalline material. Steepness of the impurity concentration gradient is thus effectively scaled as transistor size is decreased to counter increased short channel and other deleterious effects. In the case of SOI wafers greater uniformity of electrical characteristics are achieved using the high quality of semiconductor material made available therein consistent with the relatively thin active layer. In the case of double SOI, a ground plane is formed under the conduction channel which regulates the geometry of the electric field in the conduction channel with much the same functional improvements as is achieved in dual gate transistor designs.

Dependencies are inferred from the claim text.