Method of localized placement manipulation without extra latency
AssigneeCypress Semiconductor Corporation
InventorsKimihiko Nishioka, Koji Ishizaki, Masahiro Kaburaki
Life of this patent
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Abstract
A method for placement and manipulation of logic equations of a device design, comprising the steps of (A) identifying one or more logic equations of the device design with placement problems, (B) identifying one or more candidate equations of the logic equations with placement problems, and (C) re-synthesizing the one or more logic blocks of the candidate equations without adding latency to the device design.
Claims19
A method for placement and manipulation of logic equations of a device design, comprising the steps of:
- (A) identifying one or more logic blocks of said device design with placement problems and protecting functional logic blocks;
- (B) identifying one or more candidate equations of said logic blocks;
- and
- (C) re-synthesizing said one or more logic blocks of said candidate equations without increasing latency in said device design.
A method for fitting logic equations of a device design, comprising the steps of:
- (A) identifying one or more logic equations of said device design with placement problems;
- (B) re-synthesizing one or more logic blocks corresponding to one of said logic equations without adding latency and resources to said device design and protecting functional logic blocks;
- and
- (C) repeating step (B).
A method for placement and manipulation of logic equations of a device design, comprising the steps of:
- (A) identifying one or more logic blocks of said device design with placement problems;
- (B) identifying one or more candidate equations of said logic blocks and protecting functional logic equations;
- and
- (C) re-synthesizing said one or more logic blocks of said candidate equations without adding latency to said device design.
Dependencies are inferred from the claim text.