Reducing clock skew in clock gating circuits

A method comprising:

• determining a gating circuit having a gated clock net that drives a clock input of a sequential element, the sequential element receiving a first input net at a data input and generating an output net, the gating circuit having a user-defined clock net;
• and
• transforming the gating circuit to provide a second input net to the sequential element based on a cofactor condition of the gating circuit, transforming comprising:
• obtaining an enable net, and
• reconnecting the user-defined clock net and the first input net, wherein reconnecting comprises:
• disconnecting the gated clock net from clock input of the sequential element,
• connecting the user-defined clock net to the clock input of the sequential element,
• if the sequential element has an enable input, combining the enable net with an existing net connected to the enable input, the combined enable net and the existing net being connected to the enable input, and
• if the sequential element does not have the enable input and there is a library element having a library enable input and functionally equivalent to the sequential element,
• replacing the sequential element with the library element,
• reconnecting output pin and equivalent inputs of the sequential element to the library element,
• connecting the enable net to the library enable input of the library element, and
• removing the sequential element.

A computer program product of comprising:

• a machine useable medium having program code embedded therein, the program code comprising:
• computer readable program code to determine a gating circuit having a gated clock net that drives a clock input of a sequential element, the sequential element receiving a first input net at a data input and generating an output net, the gating circuit having a user-defined clock net, the computer readable program code to determine the gating circuit comprising:
• computer readable program code to collect internal gates between the gated clock net and the user-defined clock net, the computer readable program code to collect the internal gates comprising:
• computer readable program code to collect intermediate gates in a subcircuit of the gating circuit,
• computer readable program code to initialize an input set,
• computer readable program code to select an input of one of the intermediate gates, the input having a driver, and
• computer readable program code to add the input to the input set if the driver is not marked and the input is not in the input set, and
• computer readable program code to generate cofactors of a Boolean function of the gating circuit;
• and
• computer readable program code to transform the eating circuit to provide a second input net to the sequential element based a cofactor condition of the gating circuit, wherein the computer readable program code to collect the intermediate gates comprises:
• computer readable program code to perform a search of gates in the gating circuit starting from the user-defined clock net;
• computer readable program code to mark a candidate gate in the gates as an intermediate gate if the candidate gate drives one of the gated clock net and a neighboring gate that has been marked after visiting all forward neighbors of the candidate gate;
• and
• computer readable program code to stop the search when one of a primary input, the sequential element, and the gated clock net is reached.

A computer program product comprising:

• a machine useable medium having program code embedded therein, the program code comprising:
• computer readable program code to determine a gating circuit having a gated clock net that drives a clock input of a sequential element, the sequential element receiving a first input net at a data input and generating an output net, the gating circuit having a user-defined clock net;
• and
• computer readable program code to transform the gating circuit to provide a second input net to the sequential element based a cofactor condition of the gating circuit, the computer readable program code to transform comprising:
• computer readable program code to obtain an enable net, and
• computer readable program code to reconnect the user-defined clock net and the first input net;
• wherein the computer readable program code to reconnect comprises:
• computer readable program code to disconnect the gated clock net from clock input of the sequential element,
• computer readable program code to connect the user-defined clock net to the clock input of the sequential element,
• computer readable program code to combine the enable net with an existing net connected to the enable input if the sequential element has an enable input, the combined enable net and the existing net being connected to the enable input, and
• computer readable program code to replace the sequential element with a library element if the sequential element does not have the enable input and there is the library element having a library enable input and functionally equivalent to the sequential element,
• computer readable program code to reconnect output pin and equivalent inputs of the sequential element to the library element,
• computer readable program code to connect the enable net to the library enable input of the library element, and
• computer readable program code to remove the sequential element.

A system comprising:

• a processor;
• and
• a memory coupled to the processor, the memory having program code, the program code when executed by the processor causing the processor to:
• determine a gating circuit having a gated clock net that drives a clock input of a sequential element, the sequential element receiving a first input net at a data input and generating an output net, the gating circuit having a user-defined clock net, the program code causing the processor to determine the gating circuit causes the processor to:
• collect internal gates between the gated clock net and the user-defined clock net, the program code causing the processor to collect the internal gates causes the processor to:
• collect intermediate gates in a subcircuit of the gating circuit,
• initialize an input set;
• select an input of one of the intermediate gates, the input having a driver, and
• add the input to the input set if the driver is not marked and the input is not in the input set, and
• generate cofactors of a Boolean function of the gating circuit;
• and
• transform the gating circuit to provide a second input net to the sequential element based on a cofactor condition of the gating circuit;
• wherein the program code causing the processor to collect the intermediate gates causes the processor to:
• perform a search of gates in the gating circuit starting from the user-defined clock net;
• mark a candidate gate in the gates as an intermediate gate if the candidate gate drives one of the gated clock net and a neighboring gate that has been marked after visiting all forward neighbors of the candidate gate;
• and
• stop the search when one of a primary input, the sequential element, and the gated clock net is reached.

A system comprising:

• a processor;
• and
• a memory coupled to the processor, the memory having program code, the program code when executed by the processor causing the processor to:
• determine a gating circuit having a gated clock net that drives a clock input of a sequential element, the sequential element receiving a first input net at a data input and generating an output net, the gating circuit having a user-defined clock net, and
• transform the gating circuit to provide it second input net to the sequential element based on a cofactor condition of the gating circuit, wherein the program code causing the processor to transform causes the processor to:
• obtain an enable net;
• and
• reconnect the user-defined clock net and the first input net;
• wherein the program code causing the processor to reconnect causes the processor to:
• disconnect the gated clock net from clock input of the sequential element,
• connect the user-defined clock net to the clock input of the sequential element,
• combine the enable net with an existing not connected to the enable input if the sequential element has an enable input, the combined enable net and the existing net being connected to the enable input, and
• if the sequential element does not have the enable input and there is a library element having a library enable input and functionally equivalent to the sequential element,
• replace the sequential element with the library element,
• reconnect output pin and equivalent inputs of the sequential element to the library element,
• connect the enable net to the library enable input of the library element, and
• remove the sequential element.