Method and device for computing incremental checksums

A circuit comprising:

• a first memory for storing first checksum information corresponding to a data packet;
• a second memory for storing second checksum information corresponding to old information being deleted from the data packet;
• a third memory for storing third checksum information corresponding to new information being added to the data packet;
• an incremental checksum circuit, electrically coupled to the first memory, the second memory, and the third memory, for providing resulting checksum information corresponding to the data packet after deleting the old information from the data packet and adding the new information to the data packet.

A computing system comprising:

• a processor;
• a first memory for storing first checksum information corresponding to a data packet;
• a second memory for storing second checksum information corresponding to old information being deleted from the data packet;
• a third memory for storing third checksum information corresponding to new information being added to the data packet;
• and
• an incremental checksum circuit, electrically coupled to the first memory, to the second memory, and to the third memory, for providing resulting checksum information corresponding to the data packet after deleting the old information from the data packet and adding the new information to the data packet.

A communication system comprising:

• a communication network;
• and
• a data packet router, communicatively coupled to the communication network, for routing data packets across the communication network, the data packet router comprising:
• a processor;
• a first memory, electrically coupled to the processor, for storing first checksum information corresponding to a data packet;
• a second memory, electrically coupled to the processor, for storing second checksum information corresponding to old information being deleted from the data packet;
• a third memory, electrically coupled to the processor, for storing third checksum information corresponding to new information being added to the data packet;
• and
• an incremental checksum circuit, electrically coupled to the first memory, the second memory, and the third memory, for providing resulting checksum information corresponding to the data packet after deleting the old information from the data packet and adding the new information to the data packet.