US 6,643,820 B2 · Signal processing circuit with timing recovery PLL

Abstract

A signal processing circuit for processing a read signal corresponding to data read from a recording medium, such as a magnetic disc. The signal processing circuit detects a preamble data signal of the read signal. A decision feedback equalizer (DFE) generates a computation read signal by performing a predetermined computation on the read signal in accordance with a clock signal. The DFE generates first code data using the computation read signal. A code data generating circuit connected to the DFE compares the computation read signal with a first reference signal and generates second code data, which corresponds to the preamble data signal. A phase error detection circuit detects a phase error between the clock signal and the read signal using one of the first and second code data. A timing recovery PLL is connected to the phase error detection circuit and uses the detected phase error to generate the clock signal such that the phase of the clock signal matches the phase of the preamble data signal.

Claims21

Dependent claims

A method for controlling a timing recovery PLL that matches the phase of a clock signal with the phase of a preamble data signal, wherein the preamble data signal is part of a read signal corresponding to data read from a recording medium, the method comprising the steps of:

generating a computation read signal by performing a predetermined computation on the read signal;
generating a first code data using the computation read signal;
comparing the computation read signal and a first reference signal;
generating a second code data using the computation read signal;
selecting one of the first code data and the second code data on the basis of the comparison result;
detecting a phase error between the clock signal and the read signal by using the computation read signal and selected one of the first code data and the second code data;
and
matching the phase of the clock signal in accordance with the detected phase error.

5 more elements

A signal processing circuit comprising:

a computation circuit for generating a computation read signal by performing a predetermined computation on a read signal which is read in accordance with a clock signal, wherein the read signal includes a preamble data signal, and wherein the computation circuit generates first code data by using the computation read signal;
a code data generating circuit connected to the computation circuit to generate second code data based on the computation read signal;
a phase error detection circuit for detecting the phase error between the clock signal and the read signal using one of the first code data and the second code data which is selected on the basis of a comparison result between the computation read signal and a first reference signal;
and
a PLL connected to the phase error detection circuit to match the phase of the clock signal in accordance with the detected phase error.

2 more elements

Dependencies are inferred from the claim text.

Signal processing circuit with timing recovery PLL

Life of this patent

Signal processing circuit with timing recovery PLL

Life of this patent

Abstract

Claims21