Semiconductor device and semiconductor device testing method
AssigneeFujitsu Limited
InventorsHiroyoshi Tsuboi, Shinya Fujioka
Life of this patent
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Abstract
A semiconductor device which has a test mode for testing the semiconductor device, is provided with a circuit which generates a first signal based on dummy command signals which are input thereto a plurality of times, and generates a second signal which instructs entry to a corresponding test mode or an exit from a corresponding test mode based on an address signal and the first signal.
Claims6
A semiconductor device having a test mode for testing the semiconductor device, comprising:
- a circuit which generates a first signal based on dummy command signals which are input thereto a plurality of times, and generates a second signal which instructs entry to a corresponding test mode or an exit from a corresponding test mode based on an address signal and the first signal.
A semiconductor device testing method for testing a semiconductor device by switching an operation mode of the semiconductor device to a test mode, comprising the steps of:
- (a) outputting a first signal based on dummy command signals which are input a plurality of times;
- and
- (b) outputting a second signal which instructs an entry to a corresponding test mode or an exit from a corresponding test mode based on an address signal and the first signal.
Dependencies are inferred from the claim text.