Array-built-in-self-test (ABIST) for efficient, fast, bitmapping of large embedded arrays in manufacturing test

A built-in self-test (BIST) engine comprising:

• a controller responsive to a test enable signal and operative to generate and store test data in read/write memory;
• a comparator operative to compare retrieved data read from said read/write memory and said test data during a single pass test, said comparator identifying failed cycles where said retrieved data does not correspond to said test data;
• a diagnostic unit operative to store said failed cycles and being operative to store failed data and failing address during said single pass test, wherein said BIST engine stops only at each of said failed cycles during said single pass test;
• and
• a BIST clock operative to receive signals from said comparator when said failed cycles are identified by said comparator, wherein said signals gate off said BIST clock thereby stopping said BIST engine at each said failed cycles.

A method of operating a built-in self-test (BIST) engine upon read/write memory within an integrated circuit, said method comprising:

• initializing said BIST engine;
• performing a single pass test on said integrated circuit, said single pass including stops at each failed cycle;
• gating off a BIST clock on said integrated circuit when said each failed cycle is identified;
• stopping said BIST engine when said BIST clock is gated off;
• and
• storing addresses of failed memory devices during said stops.

An integrated circuit comprising read/write memory having a plurality of memory devices, each of said memory devices having a unique address, and a built-in self-test (BIST) engine, said BIST engine comprising:

• a controller responsive to a test enable signal and operative to generate and store test data in said read/write memory;
• a comparator operative to compare retrieved data read from said read/write memory and said test data during a first pass test, said comparator identifying failed cycles where said retrieved data does not correspond correctly to said test data;
• a diagnostic unit operative to store said failed cycles and being responsive to said controller regenerating and re-storing said test data in said read/write memory and operative to store failed data and failing addresses during a second pass test, wherein said BIST engine stops only at each of said failed cycles during said second pass test;
• and
• a BIST clock operative to receive signals from said comparator when said failed cycles are identified by said comparator, wherein said signals gate off said BIST clock thereby stopping said BIST engine at each said failed cycles.