Memory circuit being capable of compression test
AssigneeFujitsu Limited
InventorsAkira Kikutake, Masato Matsumiya, Satoshi Eto, Kuninori Kawabata
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Abstract
The present invention is a memory circuit which selects N number of segments out of M number of segments (N<M) during normal reading, wherein all the M number of segments are activated during a read test in order to drive a common data bus for testing by a plurality of sense buffers in the M number of segments. For this, test signals are supplied to a column decoder, and segment select signals, for activating the M number of segments, are generated in response to the test signal. In this way, a plurality of segments in a memory bank in a select status can be simultaneously selected to execute a read test, and the efficiency of a compression read test can be improved.
Claims6
A memory circuit comprising:
- M number of segments (M is an integer) each of which has a plurality of memory cells, and
- a common data bus for testing disposed commonly for said M number of segments,
- wherein N number of segments out of said M number of segments (N is an integer, and N<M) are activated during normal reading, and all of said M number of segments are activated during a compression read test in order to drive said common data bus for testing by a plurality of sense buffers in said M number of segments.
Dependencies are inferred from the claim text.