US 6,643,803 B1Granted

Emulation suspend mode with instruction jamming

AssigneeTexas Instruments Incorporated

InventorsGary L. Swoboda, David R. Matt

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Abstract

Emulation and debug circuitry is provided that can be incorporated into a variety of digital systems. A stop mode of operation is provided in which an associated processor stops processing instructions in response to a debug event. A real-time mode of operation is provided in which the processor stops processing background instructions in response to a debug event, but in which high priority interrupts are still processed. While running or suspended, the emulation circuitry can jam an instruction into the instruction register of the processor to cause processor resources to be read or written on behalf of the emulation circuitry. An embodiment of a processor core is provided that is a programmable digital signal processor (DSP) with variable instruction length, offering both high code density and easy programming. Architecture and instruction set are optimized for low power consumption and high efficiency execution of DSP algorithms, such as for wireless telephones, as well as pure control tasks.

Claims19

Dependent claims

A digital system comprising a processor, wherein the processor is operable to execute a sequence of instructions obtained from an instruction bus connected to an instruction memory circuit, wherein the processor comprises:

system resources including registers and at least one memory circuit;
an instruction pipeline operable to decode the sequence of instructions, access operands from system resources, and store results in the system resources;
test port circuitry for receiving test commands from a remote test host;
emulation circuitry for debug events connected to the test port circuitry, operable to cause the processor to enter a debug suspend state in response to a debut event and to leave the debug suspend state to resume execution of the sequence of instruction in response to a command received by the test port circuitry, wherein execution of the sequence of instructions ceases while the processor is in the debug suspend state;
and further comprising
detection circuitry operable to detect a bubble in the instruction pipeline during which no system resource is being accessed in response to executing the sequence of instructions;
and
jamming circuitry connected to the instruction pipeline operable to jam an access for a system resource in response to an access command received by the test port circuitry into the bubble detected by the detection circuitry, whereby the access of the system resources in response to the access command is performed without delaying the instruction pipeline when the processor is not in the debug suspend state.

5 more elements

A method of operating a digital system comprising a processor with system resources including registers and at least one memory circuit, comprising the steps of:

executing a sequence of instructions obtained from an instruction bus connected to an instruction memory circuit;
receiving an access command from a remote test host;
accessing the system resources in response to the access command while the processor is executing the sequence of instructions such that execution of the sequence of instructions is not discontinued by the access of the system resources;
detecting an access hole in the instruction pipeline during which no system resource is being accessed in response to executing the sequence of instructions;
and
wherein the step of accessing is enabled only when an access hole is detected so that the instruction pipeline continues execution of the sequence of instructions without interruption.

3 more elements

system resources including the instruction memory circuit and memory mapped registers connected to the processor;
test port circuitry for receiving access commands from a remote test host;
and
emulation circuitry connected to the test port circuitry;
an instruction pipeline operable to decode the sequence of instructions, access the system resources to obtain operands, and access system resources to store results;
detection circuitry operable to detect a hole in the instruction pipeline during which no system resource is being accessed during execution of the sequence of instructions;
and
wherein the emulation circuitry comprises access circuitry connected to the instruction pipeline operable to insert an access request for a system resource into the hole detected by the detection circuitry, whereby an access of the system resources in response to the an access command is performed without interrupting the instruction pipeline.

5 more elements

Dependencies are inferred from the claim text.