Semiconductor storage unit
AssigneeNEC Electronics Corporation
InventorSatoshi Utsugi
Life of this patent
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Abstract
A semiconductor storage unit is provided with a memory cell array that is sectioned into a plurality of blocks, a redundant memory cell, and a redundant memory cell selection circuit for replacing a defective cell in the memory cell array with the redundant memory cell. The redundant memory cell selection circuit is provided with n-channel MOS transistors (N00-N03) to whose gates a block selection signal (BLK) is input, p-channel MOS transistors (P0-P3) to whose gates a block selection signal (BLKB) that is reverse in logical value to the block selection signal (BLK) is input, and fuses (F0-F3) that are connected between the sources or drains of the transistors (N00-N03) and those of the transistors (P0-P3), respectively. Thereby, it is possible to reduce the number of fuses and the size of a chip.
Claims6
A semiconductor storage unit comprising:
- a memory cell array that is sectioned into a plurality of blocks;
- a redundant memory cell;
- and
- a redundant memory cell selection circuit for replacing a defective memory cell in the memory cell array with the redundant memory cell in such a manner that the replacement is correlated with a first block selection signal for selecting a prescribed block from among the plurality of blocks and a second block selection signal that is reverse in logical value to the first block selection signal, wherein the redundant memory cell selection circuit comprises:
- first field-effect transistors to whose gates the first block selection signal is input;
- second field-effect transistors to whose gates the second block selection signal is input and that are different in channel conductivity type from the first field-effect transistors;
- and
- fuses connected between the sources or drains of the first field-effect transistors and those of the second field-effect transistors.
Dependencies are inferred from the claim text.