Integrated circuit device having clock frequency changing function, computer system using the integrated circuit device and clock frequency changing method

A semiconductor device having a clock frequency changing function comprising:

• a clock generation circuit;
• means for issuing a bus transaction for changing a clock frequency to a system bus when a usage right of the system bus can be acquired;
• means for outputting a signal indicating an increase of the clock frequency, a signal indicating a decrease of the clock frequency, or a signal indicating that the clock frequency need not be changed, to a clock control bus thereby notifying another semiconductor device connected to the system bus of a clock changing operation;
• and
• means for controlling the clock generation circuit to execute a clock frequency changing operation after a predetermined time period elapses provided that a retry request is not returned from the other semiconductor device, and for changing the signal on the clock control bus to the signal indicating that the clock frequency need not be changed.

A semiconductor device having a clock frequency changing function comprising:

• a clock generation circuit;
• means for receiving a bus transaction for changing a clock frequency issued to a system bus from another semiconductor device which is connected to the system bus and acquires a usage right of the system bus;
• means for receiving a signal indicating an increase of the clock frequency, a signal indicating a decrease of the clock frequency, or a signal indicating that the clock frequency need not be changed from the other semiconductor device;
• and
• means for returning a normal response to the other semiconductor device when it is possible to change the clock frequency as indicated by the signal received, controlling the clock generation circuit to execute a clock frequency changing operation after a predetermined time period elapses, and for changing the signal on a clock control bus to the signal indicating that the clock frequency need not be changed.

A computer system comprising:

• a system bus;
• a clock control bus, which is independent of the system bus, for transmitting a signal indicating an increase of the clock frequency, a signal indicating a decrease of the clock frequency, or a signal indicating that the clock frequency need not be changed;
• and
• first and second semiconductor devices connected to each other via said system bus and said control bus, each of the semiconductor devices comprising a clock generation circuit,
• wherein said first semiconductor device issues a clock frequency changing transaction to said second semiconductor device through the system bus;
• said second semiconductor device notifies said first semiconductor device that a clock frequency can be changed when it is possible to change the clock frequency as indicated by the transaction;
• and
• said first and second semiconductor devices synchronously execute clock frequency changing operations after a predetermined time period elapses.

A computer system comprising:

• a system bus;
• a clock control bus, which is independent of the system bus;
• and
• first and second semiconductor devices connected to each other via said system bus and said control bus,
• wherein said first semiconductor device comprises:
• a first clock generation circuit;
• means for issuing a bus transaction for changing a clock frequency to the system bus when a usage right of the system bus can be acquired;
• means for outputting a signal indicating an increase of the clock frequency, a signal indicating a decrease of the clock frequency, or a signal indicating that the clock frequency need not be changed, to the clock control bus thereby notifying said second semiconductor device connected to the system bus of a clock changing operation;
• and
• means for controlling the first clock generation circuit to execute a clock frequency changing operation after a predetermined time period elapses provided that a retry request is not returned from the other semiconductor device, and for keeping the signal on the clock control bus to the signal indicating that the clock frequency need not be changed, and
• said second semiconductor device comprises:
• a second clock generation circuit;
• means for receiving the transaction for changing a clock frequency issued to the system bus from said first semiconductor device;
• means for receiving the signal indicating an increase of the clock frequency, the signal indicating a decrease of the clock frequency, or the signal indicating that the clock frequency need not be changed from said first semiconductor device;
• and
• means for returning a normal response to said first semiconductor device when it is possible to change the clock frequency as indicated by the signal received, controlling the second clock generation circuit to execute a clock frequency changing operation after the predetermined time period elapses, and for keeping the signal on the clock control bus to the signal indicating that the clock frequency need not be changed.

A semiconductor device connected to a system bus and having a clock frequency changing function, the device comprising:

• a clock generation circuit;
• means for monitoring at least first and second signals output to a clock control bus which is independent of the system bus;
• means for deasserting said second signal when it is detected, because said first signal is not asserted, that its own semiconductor device completes a preparation of a clock frequency changing operation and that another semiconductor device connected to the system bus completes the preparation of a clock frequency changing operation, and for asserting said first signal to establish synchronization after a first time period elapses;
• means for deasserting said first signal after a second time period elapses thereby confirming that synchronization is established;
• and
• means for controlling a clock control circuit to execute a clock frequency changing operation after a third time period elapses.

A semiconductor device connected to a system bus and having a clock frequency changing function, the device comprising:

• a clock generation circuit;
• means for monitoring at least first and second signals output to a clock control bus which is independent of the system bus;
• means for asserting said first signal when said first and second signals are not asserted for a first time period and its own semiconductor device completes a preparation of a clock frequency changing operation, and for deasserting said first signal after a second time period elapses;
• and
• means for detecting, because said second signal is not asserted during the second time period, that another semiconductor device connected to the system bus also completes a preparation of a clock frequency changing operation, for asserting said second signal a third time period after the first signal is deasserted, for deasserting said second signal after a fourth time period elapses after the first signal is deasserted, and controlling the clock generation circuit to execute the clock frequency changing operation when a synchronization establishment is established.