Duty cycle correction circuit with frequency-dependent bias generator
AssigneeRambus Inc.
InventorsLeung Yu, Roxanne Vu
Life of this patent
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Abstract
A duty cycle correction circuit operates by alternately speeding and slowing successive transitions of an input clock signal. By altering the rising and falling edge rates of a clock signal asymmetrically, the duty cycle of the clock signal is adjusted without shifting the DC level of the clock signal. In one embodiment, the duty cycle correction circuit includes current sources in place of resistive loads to avoid shifting the DC level of output clock signals. Frequency-dependent current sources that generate increased bias currents at higher frequency are used to achieve duty cycle correction over a broad range of input frequencies.
Claims27
An apparatus comprising:
- duty cycle detection circuitry to detect duty cycle distortion in a clock signal and to generate an error signal in response thereto;
- and
- duty cycle correction circuitry coupled to receive the error signal and configured to increase a first edge rate of the clock signal and decrease a second edge rate of the clock signal in response to the error signal to reduce the duty cycle distortion.
An apparatus comprising:
- a charge storage device coupled to be charged and discharged in response to oscillation of an input clock signal;
- control circuitry coupled to the charge storage element, the control circuitry including circuitry to detect duty cycle distortion in the input clock signal and, responsive thereto, to adjust current flowing to charge and discharge the charge storage element to increase an edge rate of the input clock signal when the input clock signal transitions between high and low levels in a first direction and to decrease an edge rate of the input clock signal when the clock signal transitions between high and low levels in a direction opposite the first direction.
An apparatus comprising:
- means for detecting duty cycle distortion in a clock signal and for generating an error signal in response thereto;
- and
- means for increasing a first edge rate of the clock signal and decreasing a second edge rate of the clock signal in response to the error signal to reduce the duty cycle distortion.
An method comprising:
- generating an error signal in proportion to duty cycle distortion in an input clock signal;
- and
- increasing a first edge rate of the input clock signal and decreasing a second edge rate of the input clock signal in response to the error signal to reduce the duty cycle distortion.
A method of reducing duty cycle distortion in an input clock signal, the method comprising:
- charging and discharging a charge storage element in response to oscillation of the clock signal;
- and
- dynamically adjusting a current flowing to charge and discharge the charge storage element to increase an edge rate of the clock signal when the clock signal transitions between high and low levels in a first direction and to decrease an edge rate of the clock signal when the clock signal transitions between high and low levels in a direction opposite the first direction.
Dependencies are inferred from the claim text.