Computer system having memory device with adjustable data clocking using pass gates

In a synchronous memory device, a method of coupling data signals from an array of memory cells to a data bus terminal, comprising:

• accepting a data signal at a data input;
• accepting a clock signal at a clock input;
• providing a delay control signal indicative of a desired delay time;
• using the delay control signal to provide a delay time to be added to the clock signal to generate a delayed clock signal;
• and
• using the delayed clock signal to control the time when the data signal is passed to the data bus terminal.

In a synchronous memory device, a method of coupling data signals from an array of memory cells to a data bus terminal, comprising:

• accepting a data signal at a data input;
• accepting a clock signal at a clock input;
• coupling the data signal to a data passing circuit;
• providing a delay control signal indicative of a desired delay time;
• using the delay control signal to select a delay time to be added to the clock signal to generate a delayed clock signal;
• and
• using the delayed clock signal to control the time when the data passing circuit couples the data signal to the data bus terminal.

A computer system comprising:

• a data input device;
• a data output device;
• an address bus;
• a data bus;
• a control bus;
• and
• computing circuitry coupled to the data input and output devices, and the data, address and control busses, the computing circuitry including:
• a data delay circuit comprising
• an external clock terminal adapted to receive an external clock signal having a first state and a second state,
• a data terminal adapted to receive a data signal,
• an adjustable time delay circuit having a plurality of control inputs each adapted to receive a respective control signal, the time delay circuit adapted to receive the external clock signal at a clock input and pass a delayed clock signal to an output terminal, the time between when the external clock signal changes states and when the delayed clock signal changes states determined by the control signals received at the control inputs, and
• a data passing circuit receiving both the data signal and the delayed clock signal, the data passing circuit adapted to pass the data signal from the data terminal to a data output terminal responsive to the delayed clock signal changing from the first to the second state.