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US 6,643,785 B1Granted
Interruption control circuit for use in an apparatus having a microcomputer
AssigneeKabushiki Kaisha Toshiba
InventorsToshiyuki Kamimura, Koichi Teraya
Life of this patent
Estimating the term…
Abstract
A CPU deactivates an A/D converter section before it stops operating in an idle mode. When any one of the keys in key matrices is pushed, the key matrix including the key pushed generates a voltage. The voltage is applied to the A/D converter section and one of buffer circuits. If the voltage is lower than the threshold voltage of the buffer circuit, the output signal of an AND circuit changes, and an interrupt-signal generating circuit generates a signal for releasing the idle mode. In response to this signal, the CPU starts operating and activates the A/D converter section.
Claims18
An interruption control circuit comprising:
- a group of key matrices, each having keys and designed to generate different voltages when the keys are operated;
- an analog-to-digital converter section for converting the voltages applied from the key matrices to digital data;
- a control section designed to activate the analog-to-digital converter section in a normal mode, deactivate the same in an idle mode, stop operating in the idle mode, and determine, in the normal mode, which key of any key matrix has been pushed, from the digital data supplied from the analog-to-digital converter section;
- a plurality of buffer circuits for receiving the voltages applied from the key matrices, respectively, each buffer circuit having a threshold voltage and designed to output a first-level signal when the voltage is equal to or higher than the threshold voltage and to output a second-level signal when the voltage is lower than the threshold voltage;
- a logic circuit for receiving signals output from the buffer circuits and generating a detection signal when the signal output from any one of the buffer circuits changes;
- and
- an interrupt-signal generating circuit connected to the logic circuit, for generating a signal for releasing the idle mode and supplying the same to the control circuit when the logic circuit generates the detection signal.
4 more elements
An interruption control circuit comprising:
- a group of key matrices, each having keys and designed to generate different voltages when the keys are operated;
- an analog-to-digital converter section for converting the voltages applied from the key matrices to digital data;
- a control section designed to activate the analog-to-digital converter section in a normal mode, deactivate the same in an idle mode, stop operating in the idle mode, and determine, in the normal mode, which key of any key matrix has been pushed, from the digital data supplied from the analog-to-digital converter section;
- a plurality of buffer circuits for receiving the voltages applied from the key matrices, respectively, each buffer circuit having a threshold voltage and designed to output a first-level signal when the voltage is equal to or higher than the threshold voltage and to output a second-level signal when the voltage is lower than the threshold voltage;
- a logic circuit for receiving signals output from the buffer circuits and generating a detection signal when the signal output from any one of the buffer circuits changes;
- an interrupt-signal generating circuit connected to the logic circuit, for generating a signal for releasing the idle mode and supplying the same to the control section when the logic circuit generates the detection signal;
- and
- a signal-supplying circuit for supplying the output signals of the buffer circuits to the control section,
- wherein the control section selects any key matrix in which at least one key has been pushed, in accordance with the output signals of the buffer circuits, and supplies a selection signal to the analog-to-digital converter section, and the analog-to-digital converter section converts the output voltage of the key matrix to digital data.
6 more elements
An interruption control circuit comprising:
- a group of key matrices, each having keys and designed to generate different voltages when the keys are operated;
- an analog-to-digital converter section for converting the voltages applied from the key matrices to digital data;
- a control section designed to deactivate the same in an idle mode, stop operating in the idle mode, and determine, in a normal mode, which key of any key matrix has been pushed, from the digital data supplied from the analog-to-digital converter section;
- a plurality of buffer circuits for receiving the voltages applied from the key matrices, respectively, each buffer circuit having a threshold voltage and designed to output a first-level signal when the voltage is equal to or higher than the threshold voltage and to output a second-level signal when the voltage is lower than the threshold voltage;
- selection circuits connected to output terminals of the buffer circuits, respectively, each for selecting the output signal of the associated buffer circuit in the idle mode;
- a logic circuit for receiving signals output from the selection circuits and generating a detection signal when the signal output from any one of the buffer circuits changes;
- an interrupt-signal generating circuit connected to the logic circuit, for generating a signal for releasing the idle mode and supplying the same to the control section when the logic circuit generates the detection signal;
- and
- an activating circuit for activating the analog-to-digital converter section in accordance with the detection signal generated by the logic circuit.
6 more elements
An interruption control circuit comprising:
- a group of key matrices, each having keys and designed to generate different voltages when the keys are operated;
- an analog-to-digital converter section for converting the voltages applied from the key matrices to digital data;
- a control section designed to deactivate the same in an idle mode, stop operating in the idle mode, and determine, in a normal mode, which key of any key matrix has been pushed, from the digital data supplied from the analog-to-digital converter section;
- a plurality of buffer circuits for receiving the voltages applied from the key matrices, respectively, each buffer circuit having a threshold voltage and designed to output a first-level signal when the voltage is equal to or higher than the threshold voltage and to output a second-level signal when the voltage is lower than the threshold voltage;
- a logic circuit for receiving signals output from the buffer circuits and generating a detection signal when the signal output from any one of the buffer circuits changes;
- an interrupt-signal generating circuit connected to the logic circuit, for generating a signal for releasing the idle mode and supplying the same to the control section when the logic circuit generates the detection signal;
- and
- a channel-selecting circuit for receiving the output signals of the buffer circuits, selecting any key matrix in which at least one key has been pushed, and outputting a selection signal,
- wherein the analog-to-digital converter section converts, to digital data, the voltage applied from the key matrices in accordance with the selection signal.
6 more elements
Dependencies are inferred from the claim text.