Branch misprediction recovery using a side memory
AssigneeIntel Corporation
InventorNicolas I. Kacevas
Life of this patent
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Abstract
A mispredicted path side memory is configured to be coupled to a stage in an instruction pipeline. As instructions advance through the pipeline, a result from the stage is stored into the mispredicted path side memory. The result is restored from the mispredicted path side memory into a pipeline stage when a branch is mispredicted.
Claims23
A method for branch misprediction recovery in a multi-stage pipelined processor, the method comprising:
- predicting at a branch, an instruction sequence predicted to be executed and an instruction sequence predicted not to be executed;
- advancing an instruction in the instruction sequence that is predicted not to be executed through a plurality of instruction pipeline stages for execution;
- storing to a mispredicted path side memory, each stage in parallel, a result of the instruction in the instruction sequence that is predicted not to be executed from the plurality of instruction pipeline stages;
- advancing an instruction in the instruction sequence predicted to be executed through the plurality of instruction pipeline stages for execution after the instruction in the instruction sequence that is predicted not to be executed is advanced;
- determining if the instruction in the instruction sequence predicted to be executed was predicted correctly;
- and
- if the instruction in the instruction sequence predicted to be executed was mispredicted, restoring in parallel the result from the storing operation into the plurality of instruction pipeline stages for continued execution.
A machine-readable medium having stored thereon a plurality of executable instructions to be executed by a processor to implement a method for branch misprediction recovery, the method comprising:
- predicting at a branch, an instruction sequence predicted to be executed and an instruction sequence predicted not to be executed;
- advancing an instruction in the instruction sequence that is predicted not to be executed through a plurality of instruction pipeline stages for execution;
- storing to a mispredicted path side memory, each stage in parallel, a result of the instruction in the instruction sequence that is predicted not to be executed from the plurality of instruction pipeline stages;
- advancing an instruction in the instruction sequence predicted to be executed through the plurality of instruction pipeline stages for execution after the instruction in the instruction sequence that is predicted not to be executed is advanced;
- determining if the instruction in the instruction sequence predicted to be executed was predicted correctly;
- and
- if the instruction in the instruction sequence predicted to be executed was mispredicted, restoring in parallel the result from the storing operation into the plurality of instruction pipeline stages for continued execution.
Apparatus for branch misprediction recovery, comprising:
- a branch prediction unit to predict, at a branch, that an instruction sequence will be executed and an instruction sequence will not to be executed;
- a plurality of instruction pipeline stages to advance an instruction in the instruction sequence that is predicted not to be executed and to advance an instruction in the instruction sequence predicted to be executed through the plurality of instruction pipeline stages for execution after the instruction in the instruction sequence that is predicted not to be executed is advanced;
- a mispredicted path side memory, coupled to the plurality of instruction pipeline stages, to store in parallel a result of the instruction in the instruction sequence that is predicted not to be executed from the plurality of instruction pipeline stages;
- a branch execution unit to determine if the instruction in the instruction sequence predicted to be executed was predicted correctly and if the instruction in the instruction sequence predicted to be executed was mispredicted, the branch execution unit restoring in parallel the result from the storing operation into the plurality of instruction pipeline stages for continued execution.
Dependencies are inferred from the claim text.