System and method for enabling selective execution of computer code

A computer system for enabling selective execution of sets of code in computer programs, comprising:

• memory for storing a computer program, said computer program having a set of code and a branch instruction;
• and
• processing circuitry configured to receive run time data indicating whether said set of code is enabled and to set a value of a mode indicator based on said run time data, said processing circuitry configured to receive and execute said branch instruction during a run of said computer program, said processing circuitry configured to branch to a first address of said memory, in response to said branch instruction and based on said value of said mode indicator, when said set of code is enabled, said processing circuitry further configured to branch to a second address of said memory, in response to said branch instruction and based on said value of said mode indicator, when said set of code is disabled,
• wherein said branch instruction includes an address identifier that identifies said first address, wherein an instruction of said set of code is stored in said memory at said first address, and
• wherein said processing circuitry, in executing said branch instruction, is configured to identify said second address based on said first address when said set of code is disabled.

A computer system for enabling selective execution of sets of code in computer programs, comprising:

• memory for storing a computer program, said computer program having a set of code and a branch instruction;
• and
• processing circuitry configured to receive run time data indicating whether said set of code is enabled and to set a value of a mode indicator based on said run time data, said processing circuitry configured to receive and execute said branch instruction during a run of said computer program, said processing circuitry configured to branch to a first address of said memory, in response to said branch instruction and based on said value of said mode indicator, when said set of code is enabled, said processing circuitry further configured to branch to a second address of said memory, in response to said branch instruction and based on said value of said mode indicator, when said set of code is disabled,
• wherein said branch instruction includes an address identifier that identifies said first address, wherein an instruction of said set of code is stored in said memory at said first address, and wherein said processing circuitry, in executing said branch instruction, is configured to flip a bit of said first address when said set of code is disabled.

A computer system for enabling selective execution of sets of code in computer programs, comprising:

• memory for storing a computer program, said computer program having a set of code and a branch instruction;
• and
• processing circuitry configured to receive run time data indicating whether said set of code is enabled and to set a value of a mode indicator based on said run time data, said processing circuitry configured to receive and execute said branch instruction during a run of said computer program, said processing circuitry configured to branch to a first address of said memory, in response to said branch instruction and based on said value of said mode indicator, when said set of code is enabled, said processing circuitry further configured to branch to a second address of said memory, in response to said branch instruction and based on said value of said mode indicator, when said set of code is disabled,
• wherein said branch instruction includes an address identifier that identifies said second address, wherein an instruction of said set of code is stored in said memory at said first address, and
• wherein said processing circuitry, in executing said branch instruction, is configured to identify said first address based on said second address when said set of code is enabled.

A computer system for enabling selective execution of sets of code in computer programs, comprising:

• memory for storing a computer program, said computer program having a set of code and a branch instruction;
• and
• processing circuitry configured to receive run time data indicating whether said set of code is enabled and to set a value of a mode indicator based on said run time data, said processing circuitry configured to receive and execute said branch instruction during a run of said computer program, said processing circuitry configured to branch to a first address of said memory, in response to said branch instruction and based on said value of said mode indicator, when said set of code is enabled, said processing circuitry further configured to branch to a second address of said memory, in response to said branch instruction and based on said value of said mode indicator, when said set of code is disabled,
• wherein said branch instruction includes an address identifier that identifies said second address, wherein an instruction of said set of code is stored in said memory at said first address, and
• wherein said processing circuitry, in executing said branch instruction, is configured to flip a bit of said second address when said set of code is enabled.

A computer system for enabling selective execution of sets of code in computer programs, comprising:

• memory for storing a computer program, said computer program having a set of code and a branch instruction;
• and
• processing circuitry configured to receive run time data indicating whether said set of code is enabled and to set a value of a mode indicator based on said run time data, said processing circuitry configured to receive and execute said branch instruction during a run of said computer program, said processing circuitry configured to branch to a first address of said memory, in response to said branch instruction and based on said value of said mode indicator, when said set of code is enabled, said processing circuitry further configured to branch to a second address of said memory, in response to said branch instruction and based on said value of said mode indicator, when said set of code is disabled,
• wherein said branch instruction includes an address identifier identifying one of said addresses, wherein said branch instruction is encoded with an expression, and wherein said processing circuitry is further configured to compute a new address for each branch instruction that is encoded with said expression and that is executed by said processing circuitry during said run of said computer program, said new address based on an address identifier included in said each branch instruction.

A method for enabling selective execution of sets of code in computer programs, comprising the steps of:

• storing a computer program in memory, said computer program having a set of code and a branch instruction, said branch instruction including an address identifier identifying a first address in said memory;
• receiving, during a run of said program, run time data indicating whether said set of code is enabled;
• setting a value of a mode indicator based on said run time data;
• identifying a second address in said memory and in response to said branch instruction;
• branching to said second address based on said value of said identifying step and said value of said mode indicator;
• and
• executing an instruction at said second address in response to said branching step,
• wherein said identifying step includes the step of flipping a bit of a bit value representing said first address.

A method for enabling selective execution of sets of code in computer programs, comprising the steps of:

• storing a computer program in memory, said computer program having a set of code and a branch instruction, said branch instruction encoded with an expression and including an address identifier identifying a first address in said memory;
• receiving, during a run of said program, run time data indicating whether said set of code is enabled;
• setting a value of a mode indicator based on said run time data;
• identifying a second address in said memory and in response to said branch instruction;
• branching to said second address based on said value of said identifying step and said value of said mode indicator;
• executing an instruction at said second address in response to said branching step;
• and
• computing a new address for each branch instruction from said computer program that is encoded with said expression and that is executed during said run of said program, said new address based on an address identifier included in said each branch instruction.