Dyadic DSP instruction processor with main and sub-operation functional blocks selected from each set of multiplier and adder

A voice and data communication system comprising:

• a packetized network;
• a first gateway coupled to the packetized network to packetize information for transmission over the packetized network;
• a second gateway coupled to the packetized network to packetize information for transmission over the packetized network;
• each of the first gateway and second gateway including a network interface with a dyadic digital signal processing instruction processor, the dyadic digital signal processing instruction processor including
• at least one signal processing unit to execute a dyadic digital signal processing instruction, the dyadic digital signal processing instruction including a main operation and a sub operation in one instruction for execution in one processor cycle, the at least one signal processing unit including,
• a first digital signal processing functional block to execute a main operation of a dyadic digital signal processing instruction, the first digital signal processing function block selected from the set of a first multiplier and a first adder;
• a second digital signal processing functional block to execute a sub operation of the dyadic digital signal processing instruction, the second digital signal processing function block selected from the set of a second multiplier and a second adder;
• data paths into and out of each of the first digital signal processing functional block and the second digital signal processing functional block selectively configured to execute the main operation and the sub operation of the dyadic digital signal processing instruction.

An application specific signal processor comprising:

• at least one core processor to execute a dyadic digital signal processing instruction, the dyadic digital signal processing instruction including a main operation and a sub operation in one instruction for execution in one processor cycle;
• at least one data memory coupled to the at least one core processor, the at least one data memory to store operands for execution with the at least one core processor;
• at least one program memory coupled to the at least one core processor, the at least one program memory to store instructions for execution by the at least one core processor;
• the at least one core processor including at least one signal processor, the at least one signal processor having
• a first digital signal processing functional block to execute the main operation of the dyadic digital signal processing instruction, the first digital signal processing function block selected from the set of a first multiplier, a compressor, a first adder, and a second adder,
• a second digital signal processing functional block to execute a sub operation of the dyadic digital signal processing instruction, the second digital signal processing function block selected from the set of a second multiplier, and a third adder, and
• multiplexers coupled to the first digital signal processing functional block and the second digital signal processing functional block, the multiplexers to selectively configure data paths of the at least one signal processor to execute the main operation and the sub operation of the dyadic digital signal processing instruction.

A signal processor for dyadic digital signal processing (DSP) instruction execution, the dyadic DSP instruction having a main op and a sub op, the signal processor comprising:

• a plurality of data busses;
• a first multiplier to selectively perform multiplication of the main op of the dyadic DSP instruction;
• a first multiplexer coupled between the plurality of data buses and the first multiplier, the first multiplexer to selectively multiplex data into the first multiplier from the plurality of data busses to execute the main op;
• a first adder to selectively perform addition of the main op of the dyadic DSP instruction;
• a second multiplexer coupled between the plurality of data buses and the first adder, the second multiplexer to selectively multiplex data into the first adder from the plurality of data busses to execute the main op;
• a second multiplier to selectively perform multiplication of the sub op of the dyadic DSP instruction;
• a third multiplexer coupled between the plurality of data buses and the second multiplier, the third multiplexer to selectively multiplex data into the second multiplier from the plurality of data busses to execute the sub op;
• a second adder to selectively perform addition of the sub op of the dyadic DSP instruction;
• and
• a fourth multiplexer coupled between the plurality of data buses and the second adder, the fourth multiplexer to selectively multiplex data into the second adder from the plurality of data busses to execute the sub op.