Programmable processor with group floating point operations

A programmable media processor comprising:

• a general purpose processor architecture, capable of operation independent of another host processor, having a virtual memory addressing unit, an instruction path and a data path;
• an external interface operable to receive data from an external source and communicate the received data over the data path;
• a cache operable to retain data communicated between the external interface and the data path;
• at least one register file configurable to receive and store data from the data path and to communicate the stored data to the data path;
• and
• a multi-precision execution unit coupled to the data path, the multi-precision execution unit configurable to dynamically partition data received from the data path to account for an elemental width of the data wherein the elemental width of the data is equal to or narrower than the data path, the multi-precision execution unit being capable of performing group floating-point operations on multiple operands in partitioned fields of operand registers and returning catenated results.