Processing system and method utilizing a scoreboard to detect data hazards between instructions of computer programs

A system for processing instructions of computer programs, comprising:

• at least one pipeline;
• a plurality of registers;
• a plurality of connections, each of said connections corresponding to a different one of said registers;
• means for maintaining a plurality of bits and for indicating via said bits which of said registers is associated with a pending write, said maintaining means configured to transmit said bits across said connections, wherein each bit transmitted across each of said connections is indicative of whether the register corresponding to said each connection is associated with a pending write;
• hazard detection circuitry configured to perform comparisons between said bits and a decoded register identifier associated with at least one instruction presently in said at least one pipeline, said hazard detection circuitry further configured to detect at least one data hazard based on said comparisons;
• and
• means for receiving from said at least one pipeline an encoded register identifier associated with said at least one instruction and for decoding said encoded register identifier into said decoded register identifier, said decoding means configured to transmit said decoded register identifier to said hazard detection circuitry and to said maintaining means, said decoded register identifier identifying at least one of said registers.

A method for processing instructions of computer programs, comprising the steps of:

• processing said instructions via at least one pipeline;
• providing a plurality of registers;
• maintaining a plurality of bits within a scoreboard, each of said bits respectively corresponding with one of said registers;
• providing a plurality of connections, each of said connections respectively corresponding with one of said registers;
• indicating, via said bits, which of said registers are associated with pending writes;
• transmitting, from said scoreboard, each of said bits across a different one of said connections;
• decoding, via a decoder, at least one register identifier associated with at least one of said instructions into a decoded register identifier, said decoded register identifier having a plurality of bits corresponding respectively with said plurality of registers and identifying at least one of said registers;
• comparing each of said transmitted bits to a respective one of said bits of said decoded register identifier;
• detecting a data hazard based on said comparing step;
• modifying one of said scoreboard bits based on said decoded register identifier;
• transmitting said at least one register identifier from said at least one pipeline to said decoder;
• and
• transmitting said decoded register identifier from said decoder to said scoreboard.

A system for processing instructions of computer programs, comprising:

• a plurality of registers;
• a plurality of connections;
• at least one pipeline;
• a scoreboard having data indicative of whether each of said plurality of registers is respectively associated with a pending write, said scoreboard configured to transmit said data across said connections;
• hazard detection circuitry coupled to said connections and configured to receive said transmitted data and to perform a comparison between said transmitted data and a decoded register identifier associated with an instruction presently in said at least one pipeline, said hazard detection circuitry further configured to detect a data hazard based on said comparison;
• and
• a decoder configured to receive, from said at least one pipeline, an encoded register identifier associated with said instruction, said decoder further configured to decode said encoded register identifier into said decoded register identifier and to transmit said decoded register identifier to said hazard detection circuitry and to said scoreboard.

A method for processing instructions of computer programs, comprising the steps of:

• processing said instructions via at least one pipeline;
• using a plurality of registers to execute said instructions;
• storing, in a scoreboard, data indicative of which of said registers is associated with a pending write;
• transmitting said data from said scoreboard;
• decoding, via a decoder, an encoded register identifier associated with one of said instructions;
• comparing said transmitted data to said decoded register identifier;
• and
• detecting a data hazard based on said comparing steps;
• transmitting said encoded register identifier from said at least one pipeline to said decoder;
• transmitting said decoded register identifier, from said decoder, to said scoreboard;
• and
• modifying said data based on said decoded register identifier.