Mechanism to extend computer memory protection schemes
AssigneeMIPS Technologies, Inc.
InventorsPeter Koch Andersson, Kevin D. Kissell
Life of this patent
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AssigneeMIPS Technologies, Inc.
InventorsPeter Koch Andersson, Kevin D. Kissell
Estimating the term…
An apparatus and method are provided that enable a central processing unit (CPU) to extend the protection schemes afforded to virtual memory beyond that which an existing translation lookaside buffer within the CPU is capable providing while at the same time preserving compatibility with legacy operating system software. The apparatus includes a translation lookaside buffer (TLB) and extended protection logic. The translation lookaside buffer (TLB) stores a plurality of TLB entries, where each TLB entry of the plurality of TLB entries has a flags field and an extended flags field. The extended protection logic is coupled to the TLB. The extended protection logic specifies legacy access restrictions according to the flags field, and specifies the extended access restrictions according to the flags field in combination with the extended flags field. Specification of the legacy access restrictions preserves compatibility with a legacy virtual page access protocol.
An apparatus for prescribing extended access restrictions for virtual memory pages, the apparatus comprising:
A mechanism in a microprocessor for enabling a translation lookaside buffer (TLB) to extend protection schemes of virtual memory pages, the mechanism comprising:
A computer program product for use with a computing device, the computer program product comprising:
A computer data signal embodied in a transmission medium, comprising:
A method for accessing a virtual memory page comprising:
Dependencies are inferred from the claim text.