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US 6,643,749 B2Granted
Interface for multi-processor
AssigneeMatsushita Electric Industrial Co., Ltd.
InventorShinichi Marui
Life of this patent
Estimating the term…
Abstract
Each of processors has an input/output port provided with a data terminal for transmitting and receiving address information and data to be transferred, a mode terminal for transmitting and receiving a mode signal indicative of whether a signal at the data terminal represents the address information or the data to be transmitted, a read/write terminal for transmitting and receiving a read/write signal indicative of a timing for each of the signal at the data terminal and a signal at the mode terminal, an input buffer and an output buffer each connected to the data terminal, a data memory pointer connected to the internal data memory, and a control circuit connected to the mode terminal and to the read/write terminal.
Claims11
An interface provided for each of a plurality of processors each having an internal data memory and connected to each other to constitute a multi-processor, the interface comprising:
- a data terminal for transmitting and receiving address information and data to be transferred;
- a mode terminal for transmitting and receiving a mode signal indicative of whether a signal at said data terminal represents the address information or the data to be transmitted;
- a read/write terminal for transmitting and receiving a read/write signal indicative of a timing for each of the signal at said data terminal and a signal at said mode terminal;
- an input buffer and an output buffer each connected to said data terminal;
- a data memory pointer connected to said internal data memory;
- and
- a control circuit connected to said mode terminal and to said read/write terminal, wherein for data transmission, said control circuit performs a control operation of:
- directing said data memory pointer to generate a read address to be given to said internal data memory based on address information for the internal data memory of an objective processor out of the plurality of processors, the address information being held in said input buffer, thereby reading data from said internal data memory, and directing said output buffer to hold the data that has been read;
- transmitting, in conjunction with said mode signal and in synchronization with said read/write signal, address information for the internal data memory of a cooperative processor out of the plurality of processors which information is held in said output buffer to said cooperative processor via said data terminal;
- and
- transmitting, in conjunction with said mode signal and in synchronization with said read/write signal, the data held in said output buffer to said cooperative processor via said data terminal and
- for data reception, said control circuit performs a control operation of:
- receiving, in conjunction with said mode signal and in synchronization with said read/write signal, address information transmitted from said cooperative processor via said data terminal and directing said input buffer to hold the address information that has been received;
- receiving, in conjunction with said mode signal and in synchronization with said read/write signal, data transmitted from said cooperative processor via said data terminal and directing said input buffer to hold the data that has been received;
- and
- directing said data memory pointer to generate, based on the address information held in said input buffer, a write address to be given to said internal data memory and thereby writing the data held in said input buffer into said internal data memory.
13 more elements
A method for interfacing a plurality of processors each having an internal data memory and connected to each other to constitute a multi-processor, each of the processors having an input/output port provided with:
- a data terminal for transmitting and receiving address information and data to be transferred;
- a mode terminal for transmitting and receiving a mode signal indicative of whether a signal at said data terminal represents the address information or the data to be transmitted;
- a read/write terminal for transmitting and receiving a read/write signal indicative of a timing for each of the signal at said data terminal and a signal at said mode terminal;
- an input buffer and an output buffer each connected to said data terminal;
- a data memory pointer connected to said internal data memory;
- and
- a control circuit connected to said mode terminal and to said read/write terminal,
- for data transmission, the method comprising the steps of:
- directing said data memory pointer to generate a read address to be given to said internal data memory based on address information for said internal data memory of an objective processor out of the plurality of processors, the address information being held in said input buffer, thereby reading data from said internal data memory, and directing said output buffer to hold the data that has been read;
- transmitting, in conjunction with said mode signal and in synchronization with said read/write signal, address information for the internal data memory of a cooperative processor out of the plurality of processors which information is held in said output buffer to said cooperative processor via said data terminal;
- and
- transmitting, in conjunction with said mode signal and in synchronization with said read/write signal, the data held in said output buffer to said cooperative processor via said data terminal,
- for data reception, the method comprising the steps of:
- receiving, in conjunction with said mode signal and in synchronization with said read/write signal, address information transmitted from said cooperative processor via said data terminal and directing said input buffer to hold the address information that has been received;
- receiving, in conjunction with said mode signal and in synchronization with said read/write signal, data transmitted from said cooperative processor via said data terminal and directing said input buffer to hold the data that has been received;
- and
- directing said data memory pointer to generate, based on the address information held in said input buffer, a write address to be given to said internal data memory and thereby writing the data held in said input buffer into said internal data memory.
14 more elements
Dependencies are inferred from the claim text.