Processing requests to efficiently access a limited bandwidth storage area
AssigneeIntel Corporation
InventorsPer H. Hammarlund, Douglas M. Carmean, Michael D. Upton
Life of this patent
Estimating the term…
Abstract
A request received from a requester to access a processor cache or register file or the like is buffered, by storing requestor identification, request type, address, and a status of the request. This buffered request may be forwarded to the cache if it has the highest priority among a number of buffered requests that also wish to access the cache. The priority is a function of at least the requestor identification, the requester type, and the status of the request. For buffered requests which include a read, the buffered request is deleted after, not before, receiving an indication that the requestor has received the data read from the cache.
Claims25
A method comprising:
- buffering a request received from a requestor to access a cache, by storing a requester identification, a request type, and a status of the request;
- forwarding the buffered request to the cache if the buffered request has the highest priority among a plurality of buffered requests to access the cache, the priority being a function of the requestor identification, the request type, and the status of the request;
- and
- if the buffered request includes a read of data from the cache, deleting the buffered request after, not before, receiving an indication that the requestor has received the data read from the cache.
A processor comprising:
- a plurality of requesters;
- a cache;
- and
- a request processor coupled to receive requests from the requestors to access the cache, the request processor having a request buffer to store a requestor identification, a request type, and a status of a request received from any of the requesters to access the cache, and selector logic to forward a buffered request to the cache if the buffered request has the highest priority among a plurality of buffered requests, each buffered request having a priority that is a function of its requester identification, request type, and status, if the buffered request includes a read of data from the cache, the request processor is to delete the buffered request after, not before, receiving an indication that the requestor has received the data read from the cache.
A computer system comprising:
- a cache;
- a processor coupled to the cache, the processor having an execution core, an instruction fetch unit, and bus interface logic to access one or both of (1) a main memory and (2) a high level cache;
- and
- a request processor coupled to receive requests from the execution core, the fetch unit, and the bus interface logic, to access the cache, the request processor having a request buffer to store a requestor identification, a request type, and a status of a request received from any one of the execution core, the fetch unit, and the bus interface unit, to access the cache, and selector logic to forward a buffered request to the cache if the buffered request has the highest priority among a plurality of buffered requests, each buffered request having a priority that is a function of its requester identification, its request type, and its status, if the buffered request includes a read of data from the cache, the request processor is to delete the buffered request after, not before, receiving an indication that the requestor has received the data read from the cache.
Dependencies are inferred from the claim text.