Optimal multi-channel memory controller system

A method of operating a Unified Memory Architecture system comprising:

• providing a memory of the Unified Memory Architecture system;
• providing a plurality of requesting devices;
• providing a plurality of channel selectors capable of receiving a command from at least one of said plurality of requesting devices for the Unified Memory Architecture system;
• providing a first memory channel coupled to each of said channel selectors to provide access to a first area of address space of the memory;
• providing at least one additional memory channel coupled to each of said channel selectors, the or each additional memory channel capable of providing access to at least one additional area of address space of the memory, each channel selector maintaining a channel identification tag that identifies the memory channel associated with the command;
• providing an arbiter capable of passing said command to a memory controller with a selector tag for use when said command is a read command to identify the channel selector that routed the command to the memory channel, wherein said arbiter is capable of using said selector tag when passing data obtained from said memory;
• and
• transmitting data to and from said memory by utilizing said arbiter, memory controller and memory channel that are used to pass said command, and using said channel identification tag to order data received from said memory.

A method of processing a memory request in a unified memory architecture system, the method comprising:

• receiving at a channel selector the request from a requester device;
• identifying one of a plurality of memory channels associated with the request, and storing at the channel selector a channel identification tag that identifies the identified memory channel;
• communicating the request to an arbiter associated with the identified memory channel, the arbiter associating with the request a selector tag to identify the channel selector from which the request was communicated;
• and
• receiving at the channel selector data from the memory channel and ordering data received from the plurality of memory channels dependent upon the channel identification tag.

A circuit to process a memory request in a unified memory architecture system, the circuit comprising:

• a channel selector to receive the request from a requestor device, wherein the channel identifies one of a plurality of memory channels associated with the request, and stores a channel identification tag that identifies the identified memory channel;
• and
• an arbiter to receive the request, the arbiter being associated with the identified memory channel and associating with the request a selector tag to identify the channel selector from which the request was communicated, and
• wherein the channel selector receives data from the memory channel and orders data received from the plurality of memory channels dependent upon the channel identification tag.