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US 6,643,742 B1Granted
Method and system for efficient cache memory updating with a least recently used (LRU) protocol
AssigneeIntel Corporation
InventorsRohit Vidwans, James A. Beavens
Life of this patent
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Abstract
A method of and system for concurrently processing multiple memory requests. The first and second memory requests contain a linear address. A search for the cache entry in a cache block is issued in response to the linear address. After locating the cache entries associated with the memory requests, there is an update of the least recently used status for the cache entries with reference to the memory requests.
Claims12
A method for processing multiple memory read requests:
- receiving a first memory read request comprising a first linear address;
- receiving a second memory read request comprising a second linear address;
- reading from a first and second cache entry in a cache block in a memory, the first and second linear addresses pointing to the first and second cache entries;
- reading a least recently used status and a valid status for a first and second cache;
- and
- updating the least recently used status for the cache block based at least in part to a pseudo-random logic, wherein the pseudo-random logic is to support a first and second hit vector with a three bit least recently used status register, wherein only two bits are analyzed and one bit is a don't care, and the pseudo-random logic is to determine an output mask.
3 more elements
A system comprising:
- a processor;
- a cache coupled to the processor, the cache having stored therein a first array of entries;
- a logic unit coupled to the processor and the cache to receive a memory request from the processor, select an entry from a second array and alter a status of the entry in the second array in response thereto, the logic unit comprising:
- a plurality of registers to store a plurality of status bits and valid bits corresponding to the entries in the second array;
- a circuit to receive the memory request and to modify the plurality of status bits based at least in part to a pseudo random logic, the logic unit to read the plurality of status bit and valid bits for every read cycle of one of the entries, and
- wherein the pseudo-random logic is to support a first and second hit vector with a three bit least recently used status register, wherein only two bits are analyzed and one bit is a don't care, and the pseudo-random logic is to determine an output mask.
3 more elements
Dependencies are inferred from the claim text.