Random replacement generator for a cache circuit
AssigneeLSI Logic Corporation
InventorStefan Auracher
Life of this patent
Estimating the term…
Abstract
A cache may comprise a memory and control logic. The memory may be configured for storing data buffered by the cache. The control logic may be configured controlling accesses to the memory. The control logic may comprise a pseudo-noise generator and a trigger device. The pseudo-noise generator may be configured for generating a pseudo-random number representing, for a miss access requiring allocation, which of a plurality of possible addresses in the memory to use for the allocation. The trigger device may be configured for controlling a cycle of the pseudo-noise generator to output the pseudo-random number therefrom.
Claims21
A cache comprising:
- a memory for storing data buffered by said cache;
- control logic for controlling accesses to said memory, wherein said control logic comprises:
- a pseudo-noise generator for generating a pseudo-random number representing, for a miss access requiring allocation, which of a plurality of possible addresses in said memory to use for said allocation;
- and
- a trigger device for controlling a cycle of said pseudo-noise generator to output said pseudo-random number therefrom.
A method of block replacement in a cache, comprising the steps of:
- (A) detecting a block replacement condition in said cache;
- (B) generating a pseudo-random number from a pseudo-noise circuit in response to said detecting;
- and
- (C) replacing a block of said cache as determined by said pseudo-random number.
A cache comprising:
- means for detecting a block replacement condition in said cache;
- pseudo-random noise means for generating a pseudo-random number in response to said means for detecting;
- and
- means for replacing a block of said cache as determined by said pseudo-random number.
Dependencies are inferred from the claim text.