Cache lock device and method therefor

In a cache lock device comprising a main memory, a cache memory formed by arranging a plurality of ways composed of a collection of a plurality of entries consisting of at least a tag memory array, a data memory array, a valid bit array, and an LRU bit array, where a lock bit array is supplied to each entry constituting at least a part of the ways, and a CPU which outputs the address of data to be transferred to a corresponding cache memory on said main memory in response to a cache lock instruction, a load/store instruction or the like, the cache lock device composed of an entry selection circuit which, in transferring data to be transferred from the main memory to the cache memory, selects from respective ones of the plurality of ways those entries having the same entry number as an index value of an index part constituting data to be transferred in response to a load instruction or a storage instruction, a lock bit detection circuit which detects whether the lock bit array is supplied to each of the plurality of selected entries and outputs a discrimination signal, a valid bit decision circuit which judges whether a valid bit in the entry is a second value when the discrimination signal from the lock bit detection circuit indicates that there is a lock bit and its value is the second value, a data overwrite disable means which inhibits the overwrite on the data in the data part constituting the data desired to be transferred to the data part of the entry when the discrimination signal of the valid bit discrimination circuit indicates that the valid bit in the entry is the second value, a valid bit rewrite circuit which permits overwrite of data on the data part constituting the data to be transferred to the data part of the entry and rewrite the bit value of the valid bit in the valid bit array of the entry to the second value when the value of the lock bit in the specified entry is the second value and when a tag value of a tag part of the selected entry agrees with the tag value of the tag part constituting the data to be transferred and the valid bit value in the valid bit array is a first value, and an LRU output conversion circuit which converts the LRU bit value to the first value.

In a cache lock device comprising a main memory, a cache memory formed by arranging a plurality of ways composed of a collection of a plurality of entries consisting of at least a tag memory array, a data memory array, a valid bit array, and an LRU bit array, and a CPU which outputs the address of a corresponding data on said main memory in response to a cache lock instruction, a load instruction, a store instruction or the like, a cache lock method, employed in transferring data to be made resident in the cache memory, comprising a first step of selecting data to be transferred to the cache memory and extracting an index value of a designated address, a second step of selecting from each way an entry having the same entry number as an index value of the data to be transferred to the cache memory, a third step of discriminating for each of selected entries whether it has a lock bit LB, a fourth step, when it is found in the third step that there exist entries having a lock bit LB among the selected entries, of judging whether the lock bit LB is a second value or a first value, a fifth step, when it is found in the fourth step that the lock bit LB of the selected entry is the second value, of comparing the value of a tag part of the entry with a tag value of the designated address, a sixth step, when it is found in the fifth step that the lock bit LB of the entry is the second value and the comparison result of the tag values is in agreement, of judging whether the value of the valid bit of the entry is the second value or the first value, a seventh step, when it is found in the sixth step that the value of the lock bit is the second value but the comparison result of the tag values is in disagreement or the value of the valid bit is the second value, of masking the LRU output of the entry to the first value to inhibit the overwrite on the entry, an eighth step, when it is found in the sixth step that the value of the lock bit is the second value, the comparison result of the tag values is in agreement, and the value of the valid bit is the first value, of setting the LRU output of the entry to the second value, and masking the LRU outputs of the other selected entries to the first value, to make the entry an object of overwriting, a ninth step of selecting the entry with the largest LRU output from among the selected entries, and a tenth step of executing the overwrite of data to the entry selected in the ninth step, and writing the second value to the valid bit.