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US 6,643,733 B2Granted
Prioritized content addressable memory
AssigneeIntel Corporation
InventorHaitham Akkary
Life of this patent
Estimating the term…
Abstract
A prioritized content addressable memory having an at most one hit property despite the presence of redundant values stored therein. Redundant values within the content addressable memory are prioritized prior to performing value matching. Value matching of input data is performed only against any unique values and any highest ranked redundant value stored in the content addressable memory.
Claims13
A method of searching a content addressable memory, comprising:
- prior to a search:
- identifying redundant values stored within the content addressable memory,
- ranking occurrences of the redundant values according to a most-recently allocated priority scheme,
- disabling value matching logic of memory entries associated with redundant values that are ranked other than highest according to the priority scheme, and during a search, searching value matching logic of enabled memory entries.
1 more element
A content addressable memory, comprising:
- a plurality of memory entries to store data, each memory entry having value matching logic, and
- a priority matrix, having matrix entries coupled to value matching logic of respective memory entries in the content addressable memory, the matrix entries comprising a plurality of flags,
- wherein, for any matrix entry having a flag that is marked, the matrix entry causes the value matching logic of the associated memory entry to be disabled,
- further comprising means for marking flags in matrix entries for which the corresponding memory entries store data that is both redundant to other data stored by the content addressable memory and ranked other than highest according to some priority scheme.
1 more element
A content addressable memory, comprising:
- a plurality of memory entries and a square priority matrix, having row entries associated with each memory entry, each row having columnar flag positions associated with each other memory entry,
- a plurality of disabling circuits, each to disable the value matching logic of a respective memory entry when flags are active in a respective row of the priority matrix, and
- a controller to activate, for memory entries that store redundant values of data, flags in columnar flag positions associated with other memory entries that store the same redundant value of data and are ranked higher according to a predetermined priority scheme.
Dependencies are inferred from the claim text.