Delayed read/write scheme for SRAM interface compatible DRAM
AssigneeEtron Technology, Inc.
InventorJeng-Tzong Shih
Life of this patent
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Abstract
A method of internally executing an externally initiated access to a dynamic memory array including a plurality of dynamic memory cells, wherein the dynamic memory cells require periodic refreshing, is achieved. The method comprises, first, determining if an external access to the dynamic memory array has been initiated. Second, a waiting period of RW idle time is inserted. The RW idle time comprises a sum of a row access time plus a pre-charge time. A pending refresh is performed during said RW idle time. A pending write access may be performed during the RW idle time. Finally, the external access is internally executed in the dynamic memory array after the RW idle time.
Claims19
A method of internally executing an externally initiated access to a dynamic memory array including a plurality of dynamic memory cells wherein said dynamic memory cells require periodic refreshing, said method comprising:
- determining if an external access to said dynamic memory array has been initiated;
- thereafter waiting a RW idle time wherein said RW idle time comprises a sum of a row access time plus a pre-charge time and wherein a pending refresh is performed during said RW idle time and further comprising:
- detecting an address skew comprising said external access initiated by a transition of an address bus and said address bus changing state during said step of waiting a RW idle time;
- and restarting said step of waiting a RW idle time each time said address skew is detected;
- and
- restarting said step of waiting a RW idle time when a dummy read is detected;
- and
- thereafter internally executing said external access to said dynamic memory array.
A method of internally executing an externally initiated access to a dynamic memory array including a plurality of dynamic memory cells wherein said dynamic memory cells require periodic refreshing, said method comprising:
- determining if an external access to said dynamic memory array has been initiated;
- thereafter waiting a RW idle time wherein said RW idle time comprises a sum of a row access time plus a pre-charge time and wherein a pending refresh is performed during said RW idle time and further comprising:
- detecting a dummy read comprising said external access initiated by a transition of an address bus and a write enable signal changing from a read state to a write state during said step of waiting a RW idle time;
- and
- restarting said step of waiting a RW idle time when said dummy read is detected;
- and
- thereafter internally executing said external access to said dynamic memory array.
A circuit for internally executing an externally initiated access to a dynamic memory array including a plurality of dynamic memory cells wherein said dynamic memory cells require periodic refreshing, said circuit comprising:
- a synchronizing clock generator that generates a sync clock from an external access signal;
- a re-triggerable delay generator that generates a delayed sync pulse from said sync clock wherein said delayed sync pulse trails said sync clock by a RW idle time comprising a sum of a row access time plus a pre-charge time;
- a read/write arbiter generating a refresh enable signal from said sync clock, said delayed sync pulse, and a refresh clock wherein said refresh enable signal is enabled during said RW idle time when said refresh clock is enabled;
- a wordline control and timer circuit that generates a wordline active signal and a bitline active signal from said delayed sync pulse and said refresh enable signal;
- and
- a row address multiplexer that selects between an externally requested address and an internal refresh address based upon said refresh enable signal wherein a pending refresh is performed during said RW idle time and wherein said external access time to said dynamic memory array is internally executed after said RW idle.
Dependencies are inferred from the claim text.