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US 6,643,716 B2Granted
Method and apparatus for processing serial data using a single receive fifo
AssigneeIntel Corporation
InventorsMikal C. Hunsaker, Darren L. Abramson, Rajesh Raman, Bret T. Connell
Life of this patent
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Abstract
The present invention discloses a method and apparatus for processing a packet of data received by a first-in-first-out (FIFO). In one embodiment, a message in the packet of data is recognized. Based on a plurality of control bits encoded in the message, a delimiting condition in the packet of data is determined. An operation is performed which is responsive to the delimiting condition. The operation controls the transfer of the packet of data from the FIFO to a memory.
Claims30
A method comprising:
- determining if a quadlet in a receive packet of data is a message quadlet, the packet of data being received by a first-in-first-out (FIFO);
- determining a delimiting condition in the message quadlet from a plurality of control bits encoded in the message quadlet;
- and
- performing an operation responsive to the delimiting condition, the operation controlling a transfer of data from the receive FIFO to a memory.
1 more element
An apparatus comprising:
- a receive first-in-first-out (FIFO) to store a packet of data;
- and
- a decoder and gating circuit coupled to the FIFO memory, the decoder and gating circuit determining if a quadlet in the packet of data is a message quadlet, the decoder and gating circuit determining a delimiting condition in the message quadlet from a plurality of control bits encoded in the message quadlet and performing an operation responsive to the delimiting condition, the operation controlling a transfer of data from the receive FIFO to a memory.
A system comprising:
- a first bus;
- a processor coupled to the bus;
- a memory coupled to the processor;
- and
- a bridge coupled to the first bus and a second bus via a physical link device, the bridge managing a transfer of a packet of data between the second bus and the processor, the bridge comprising:
- a receive first-in-first-out (FIFO) to store the packet of data, and
- a decoder and gating circuit coupled to the receive FIFO memory, the decoder and gating circuit determining if a quadlet in the packet of data is a message quadlet, the decoder and gating circuit determining a delimiting condition in the from a plurality of control bits encoded in the message quadlet and performing an operation responsive to the delimiting condition, the operation controlling a transfer of data from the receive FIFO to the memory.
4 more elements
Dependencies are inferred from the claim text.