US 6,643,713 B2 · Apparatus has a microprocessor including DSP and a CPU integrated with each other as a single bus master

Abstract

A low cost, a low power consumption and a small size are three very important factors for a mobile communication terminal. A great problem is posed by the conventional technique using a DSP and a CPU independent of each other which requires two external memory systems. Also, two peripheral units are required for data input and output of the DSP and CPU. As a result, an extraneous communication overhead occurs between the DSP and the CPU. The invention realizes a mobile communication terminal system by a DSP/CPU integrated chip comprising a DSP/CPU core (500) integrated as a single bus master, an integrated external bus interface (606) and an integrated peripheral circuit interface. The memory systems and the peripheral circuits of the DSP and the CPU can thus be integrated to realize a mobile communication terminal system low in cost and power consumption and small in size.

Claims15

Dependent claims

A terminal apparatus comprising:

a microprocessor having a DSP and a CPU integrated with each other as a single bus master, and an internal memory space and an external memory space integrated as a single memory space,
wherein the DSP includes a plurality of internal memories and a plurality of buses for connecting said internal memories for executing a non-recursive filter operation constituting a basic operation of a digital signal processing,
wherein said CPU is capable of executing a basic instruction for any of such operations as calculation, internal memory access and data transfer, and
wherein said CPU includes an instruction decoder to decode instructions for both said CPU and said DSP.

1 more element

A terminal apparatus for effecting radio communication by exchanging data with a base station, comprising:

a data processing unit including a central processing unit and a digital signal processor, the data processing unit for executing programs stored in memory;
and
a memory including an area storing a first program for performing a speech encoding/decoding process, an area storing a second program for performing the speech decoding process, n area storing a third program for performing the channel decoding process, an area storing a fourth program for controlling the communication protocol with the base station, and an area storing a fifth program for controlling the interface wit the user,
wherein said digital signal processor utilizes the first to third programs,
wherein said central processing unit utilizes the fourth and fifth programs,
wherein each of said areas of said memory is arranged in an address space of said data processing unit, and
wherein said CPU includes an instruction decoder to decode instructions comprising the first to fifth programs.

4 more elements

Dependencies are inferred from the claim text.

Apparatus has a microprocessor including DSP and a CPU integrated with each other as a single bus master

Life of this patent

Apparatus has a microprocessor including DSP and a CPU integrated with each other as a single bus master

Life of this patent

Abstract

Claims15