Digital arithmetic integrated circuit

A digital arithmetic integrated circuit, comprising:

• an arithmetic data storing memory configured to store and output first and second arithmetic data strings, the first arithmetic data string being divided into 1st through nth m-bit words, and the second arithmetic data string being divided into 1st through kth m-bit words, wherein k, m, and n are integers greater than 1, said arithmetic data storing memory comprising a first unit and a second unit, each of said first and second units being configured not to store and output said first and second arithmetic data strings as single units, but to store and output said 1st through nth and 1st through kth m-bit words of said first and second arithmetic data strings, respectively, in units of m-bit words;
• a first arithmetic operand storing register configured to reconstruct the first arithmetic data string as a first operand from n m-bit words outputted from said first unit, and to store and output the first operand;
• a second arithmetic operand storing register configured to reconstruct the second arithmetic data string as a second operand from k m-bit words outputted from said second unit, and to store and output the second operand;
• an arithmetic logic unit configured to execute an arithmetic operation based on the first and second operands output by said first and second arithmetic operand storing registers, and to output arithmetic results of the arithmetic operation;
• and
• an arithmetic result storing register configured to store the arithmetic results output by said arithmetic logic unit,
• wherein each of said first and second units have m data circuits, each data circuit comprising a memory cell array and a column selector, said memory cell array outputting a plurality of data from memory cells selected by a low decoder based on an address signal applied thereto, said column selector selecting and outputting one of the plurality of data according to said address signal, thereby each unit outputs m-bit word length data according to each address signal, one of said first and second units outputting said 1st though nth m-bit word length data items as said first arithmetic data string in n address cycles, and the other of said first and second units outputting said 1st through kth m-bit data items as said second arithmetic data string in k address cycles, each unit being arranged so as not to output n m-bit word length data or k m-bit word length data in one address cycle, but to output only m-bit word length data in one address cycle.