Duty cycle corrector for a random number generator

A duty cycle corrector circuit to generate a corrected bit stream from a random bit stream output of a random bit source, the duty cycle corrector circuit comprising:

• a first storage circuit to receive and store a first bit of a pair of bits of the random bit stream;
• a second storage circuit coupled serially to the first storage circuit to receive and store a second bit of the pair of bits;
• a compare circuit coupled to the first storage circuit and the second storage circuit to compare the pair of bits to determine if the pair of bits are different;
• validation logic circuit coupled to the first and second storage circuits and the compare circuit, the validation logic circuit to discard the pair of bits if the bits are the same, but to select respective one of the pair of bits based on the order of the bits, if the bits are different;
• and
• a timing circuit coupled to the validation logic circuit to discard every Xth bit from the random bit stream determined by a modulo-X counter to reduce autocorrelation between bits.

A computer comprising:

• a network interface device operable to send and receive messages on a network medium;
• and
• an encryption/decryption circuit operable to encode and decode messages transferred on the network medium, said encryption/decryption circuit having a random number generator operable to produce a random bit stream, said random number generator comprising:
• (a) a first storage circuit to receive and store a first bit of a pair of bits of the random bit stream;
• (b) a second storage circuit coupled serially to the first storage circuit to receive and store a second bit of the pair of bits;
• (c) a compare circuit coupled to the first storage circuit and the the second storage circuit to compare the pair of bits to determine if the pair of bits are different;
• (d) validation logic circuit coupled to the first and second storage circuits and the compare circuit, the validation logic circuit to discard the pair of bits if the bits are the same, but to select respective one of the pair of bits based on the order of the bits, if the bits are different;
• and
• (e) a timing circuit coupled to the validation logic circuit to discard every Xth bit from the random bit stream determined by a modulo-X counter to reduce autocorrelation between bits.