Frequency detection circuit for clock recovery
AssigneeRockwell Scientific Company
InventorsKen D. Pedrotti, Alistair J. Price
Life of this patent
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Abstract
A frequency detector is configured to provide reliable acquisition by a clock recovery and data regeneration circuit. A preferred frequency detector utilizes the output characteristics of a phase detector to determine a frequency difference between the recovered clock signal and the incoming data signal. The frequency detector then outputs a signal representing the frequency difference to a control device, preferably to a voltage-controlled oscillator (VCO). Upon receiving the frequency difference signal, the control device, preferably operating within a controlled-feedback loop, will begin to adjust the underlying clock frequency to approximate the incoming data frequency.
Claims33
A clock recovery circuit having a phase locked loop for recovering an underlying clock signal from an input data stream, said clock recovery circuit comprising:
- a phase detector for providing an output signal having characteristics representative of the frequency difference between the frequency of the underlying clock signal and the frequency of the input data stream;
- a frequency detector, said frequency detector comprising a differentiator, a positive peak detector and a negative peak detector, said frequency detector responsive to said output signal of said phase detector, for providing an output signal corresponding to a magnitude of the frequency difference;
- and
- an integrator, responsive to said output signal of said frequency detector, for providing a slowly varying bipolar voltage output signal proportional to the frequency difference.
A frequency detector for providing a frequency difference signal for use with a clock extraction and data regeneration circuit, said frequency detector comprising:
- a differentiator, responsive to an input signal representative of the frequency difference between the frequency of an underlying clock signal and the frequency of an incoming data signal, for providing a corresponding differentiated output signal;
- and
- a pair of peak detectors responsive to the differentiated output signal, for providing an output voltage signal representative of said frequency difference to facilitate the frequency acquisition through a control device of the clock extraction and data regeneration circuit, wherein said pair of peak detectors comprises a positive peak detector and a negative peak detector for determining the polarity of pulses of said differentiated output signal.
A clock extraction and data regeneration circuit for recovering an underlying clock signal from an incoming data signal, said clock extraction and data regeneration circuit comprising:
- a first order phase locked loop comprising:
- a phase detector for determining phase of the incoming data signal, and for providing an output signal having characteristics corresponding to the frequency difference between the frequency of said underlying clock signal and the frequency of said incoming data signal;
- a loop filter having a defined bandwidth;
- and
- a voltage-controlled oscillator for tracking the phase of the incoming data signal;
- and
- a first order frequency detector loop comprising:
- a differentiator, responsive to said output signal of said phase detector, for providing a differentiated output signal indicative of the frequency difference of the underlying clock signal and the incoming data signal;
- a pair of peak detectors for determining the polarity of said output signal of said differentiator;
- and
- an integrator, responsive to an output signal from said pair of peak detectors, for providing a slowly varying bipolar voltage to the voltage controlled oscillator;
- wherein:
- said first order frequency detector loop facilitates through said voltage-controlled oscillator locking of the first order phase locked loop over a frequency acquisition range exceeding the defined bandwidth of the loop filter.
A frequency detector for generating an output voltage representing the difference in frequency between a clock signal and an input signal, said frequency detector comprising:
- a differentiator, responsive to said input signal, for generating an output signal corresponding to said difference in frequency:
- and
- a pair of peak detectors, coupled in parallel, for generating said output voltage in response to said output signal of said differentiator wherein said pair of peak detectors comprises a positive peak detector and a negative peak detector for determining the polarity of pulses of said differentiated output signal.
Dependencies are inferred from the claim text.