DC offset and bit timing system and method for use with a wireless transceiver
AssigneeWidcomm, Inc.
InventorsHsiang-Tsuen Hsieh, Jyothis S. Indirabhai
Life of this patent
Estimating the term…
Abstract
An offset estimation and bit timing system and method configured to detect a DC offset in a received signal is disclosed herein. The inventive system includes a first circuit for receiving and correlating a transmitted signal and generating a trigger signal in response thereto. A second circuit accumulates the received signal and provides a second signal on receipt of the trigger signal. The second signal is then converted to an offset error signal. The error signal is converted to analog and used as a reference input for an A/D converter. As an alternative, the error signal may be used to adjust the signal output by an intermediate frequency downconversion stage.
Claims11
A system for estimating an offset in a signal comprising:
- first means for receiving and correlating a first signal and generating a trigger signal in response thereto, wherein said first means further includes:
- means for digitizing said first signal to provide a digital input signal in response to an analog reference signal, said means for digitizing comprising an analog to digital converter having a sampling rate of N samples per bit period,
- means for correlating said digital input signal to provide a correlated output signal,
- means for identifying a peak in said correlated output signal and providing said trigger signal in response thereto, and
- means for finding an edge in said correlated output signal and providing said trigger signal in response thereto;
- second means for accumulating said first signal and providing a second signal on receipt of said trigger signal;
- and
- third means for converting said second signal to an offset error signal.
A wireless receiver adapted to estimate a direct current offset in a received signal, said receiver, being included within a system having a wireless transmitter adapted to transmit a first signal with a predetermined bit pattern therein for a least a portion thereof, said receiver comprising:
- first means for receiving and correlating a first signal and generating a trigger signal in response thereto, said first means including:
- an analog to digital converter having a sampling rate of N samples per bit period for digitizing said first signal to provide a digital input signal in response to an analog reference signal and
- means for correlating said digital input signal to provide a correlated output signal, said means for correlating further including means for identifying a peak in said correlated output signal and means for finding an edge in said correlated output signal and providing said trigger signal at a time T=N/2 after a time of identification of said peak in response thereto;
- second means for accumulating said first signal and providing a second signal on receipt of said trigger signal, said second means including a sliding window accumulator;
- and
- third means for converting said second signal to an offset error signal, said third means further including means for converting said error signal to said analog reference signal.
Dependencies are inferred from the claim text.