Coding method and apparatus
AssigneeInmarsat, Ltd.
InventorsWade Nicholas Farrell, Mark Rice
Life of this patent
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Abstract
A parallel concatenated coder (20) outputs a sequence of data sets in which earlier data sets contain data bits (d) and non-interleaved parity bits (p) without interleaved parity bits (q), while later data sets include the interleaved parity bits (q). Each data set is modulated as one symbol. The output format partially overcomes the delay incurred by interleaving the parity bits (q), with a substantially even distribution of data and parity bits in the sequence of data sets. The delay may be reduced further by interleaving with an index constraint.
Claims23
A coding and modulation method for digital data, comprising:
- receiving an input sequence of data bits;
- encoding sad input sequence to generate a first encoded sequence of data bits;
- interleaving said input sequence to create an interleaved sequence of data bits;
- encoding said interleaved sequence of data bits to generate a second encoded sequence of data bits;
- and
- modulating a sequence of data sets each including at least one of a data bit derived from said input sequence, a first parity bit derived from said first encoded sequence and a second parity bit derived from said second encoded sequence,
- wherein during an earlier period each of a plurality of said data sets includes at least one said data bit and one said first parity bit but does not include any said second parity bits,
- and during a later period each of a plurality of said data sets includes at least one said second parity bit.
Apparatus for modulating digital data, comprising:
- a first encoder for encoding an input sequence of data bits to generate a first encoded sequence of data bits;
- an interleaver for interleaving said input sequence of data bits to generate an interleaved sequence of data bits;
- a second encoder for encoding said interleaved sequence of data bits to generate a second encoded sequence of data bits;
- and
- a modulator for modulating a sequence of data sets each including at least one of a data bit derived from said input sequence, a first parity bit derived from said first encoded sequence and a second parity bit derived from said second encoded sequence,
- such that during an earlier period each of a plurality of said data sets includes at least one said data bit and one said first parity bit but does not include any said second parity bits,
- and during a later period each of a plurality of said data sets includes at least one said second parity bit.
A method of modulating a systematic code word including data bits and interleaved parity bits derived from said data bits via an intermediate interleaving step, wherein the modulation of the first of said parity bits is delayed by a plurality of modulation symbol periods relative to that of the first of said data bits, and the period over which the data bits are modulated overlaps the period over which the parity bits are modulated.
Apparatus for modulating a systematic code word including data bits and interleaved parity bits derived from said data bits via an intermediate interleaving step, characterised by means for delaying the modulation of the first of said parity bits by a plurality of modulation symbol periods relative to that of the first of said data bits, such that the period over which the data bits are modulated overlaps the period over which the parity bits are modulated.
Dependencies are inferred from the claim text.