Distributed control merged buffer ATM switch

A method for routing cells through a switch having a plurality of input ports, a plurality of output ports, and a plurality of merged buffers, each of the merged buffers including an output buffer, an input buffer, and a controller, the method comprising:

• receiving cells of a data packet from a source at the input ports;
• routing each of the cells to one of the output buffers or one of the input buffers;
• storing cells in the output buffers for transmission by a corresponding one of the output ports;
• temporarily storing, the cells in the input buffers for rerouting to at least another one of the output ports;
• rerouting, by the controllers, the cells from the input buffers to the output buffers;
• and
• transmitting the cells stored in the output buffers from the output ports.

A system for routing cells through a switch, comprising:

• means for receiving cells of a plurality of data packets;
• means for outputting the cells in an order in which the receiving means received the cells;
• means for storing cells for transmission by a corresponding one of the outputting means;
• means for temporarily storing cells for rerouting to at least another one of the outputting means;
• and
• means for rerouting the temporarily stored cells to the storing means.

In a system that routes cells received at a plurality of input ports to a plurality of output ports, a plurality of merged buffers that temporarily store the cells for the output ports, each of the merged buffers comprising:

• an output buffer that stores cells for transmission by a corresponding one of the output ports;
• an input buffer that temporarily stores cells for rerouting to at least another one of the output ports;
• and
• a controller that reroutes the cells stored in the input buffer to output buffers corresponding to other ones of the output ports.

A routing vector data structure for guiding one of a plurality of cells of a data packet through a switch having input and output ports, comprising:

• an input port number that identifies an input port that received the cell;
• a sequence number that identifies a position of the cell within the data packet;
• an output port number that identifies an output port from which the cell is to be transmitted;
• and
• a misrouted cell sequence number that identifies the sequence of the cell routed to a buffer of an output port other than the output port identified by the output port number.

A method for routing a plurality of cells through a switch that operates under a clock cycle having first and second time slots, the switch including a plurality of input ports, a plurality of output ports, and a plurality of merged buffers, each of the merged buffers including an input buffer, an output buffer, and a controller, the method comprising:

• during the first time slot,
• receiving cells of a plurality of data packets at the input ports,
• routing each of the cells to one of the output buffers or one of the input buffers,
• storing the cells in the output buffers for transmission by a corresponding one to of the output ports,
• temporarily storing the cells in the input buffers for rerouting to at least another one of the output ports, and
• outputting the cells stored in the output buffers from the output ports;
• and during the second time slot,
• selecting, by the controllers, cells stored in the input buffers,
• rerouting each of the selected cells to one of the output buffers or one of the input buffers,
• storing the cells in the output buffers for transmission by the corresponding output ports, and
• temporarily storing the cells in the input buffers for rerouting to at least another one of the output ports.

A method for routing a plurality of cells within a switch having input ports, output ports, and merged buffers, each of the merged buffers including an input buffer, an output buffer, and a controller, the method comprising:

• receiving the cells at the input ports, each of the cells having a sequence within a data packet;
• generating routing vectors for the cells;
• routing a first set of the cells to an output buffer based on its routing vector and a second set of cells to an input buffer different from its routing vector;
• storing the cells in the first set of cells in respective output buffers;
• temporarily storing the cells in the second set of cells in respective input buffers;
• selecting cells from the input buffers;
• rerouting the selected cells based on their routing vectors;
• repeating the routing, storing, temporarily storing, selecting, and rerouting steps until all of the cells are stored in output buffers based on their routing vectors;
• and
• outputting the cells stored in the output buffers from the output ports.

A method for routing a plurality of cells within a switch having input ports, output ports, and merged buffers, each of the merged buffers including an input buffer, an output buffer, and a controller, the method comprising:

• receiving the cells at the input ports, each of the cells having a sequence within a data packet;
• identifying at least one of the received cells as a multicast cell;
• generating a routing vector for the multicast cell that identifies a group of the output ports;
• routing the multicast cell to an input buffer based on the input port receiving the multicast cell;
• and
• temporarily storing the multicast cell in the input buffer;
• rerouting the multicast cell from the input buffer to output buffers corresponding to the output ports in the group;
• and
• transmitting the multicast cell from the output ports in the group.

A switch comprising:

• a plurality of input ports that receive cells of a data packet from a source;
• a plurality of output ports that output the cells in an order in which the input ports receive the cells;
• and
• a plurality of distributed merged buffers, corresponding to the plurality of output ports, that temporarily store the cells received by the input ports for at least one of transmission by a corresponding one of the output ports and rerouting to at least another one of the output ports.