Message based packet switch based on a common, generic bus medium for transport

A packet switch comprising a switching unit (SU) for switching packets between network links, and a computing unit (CU) connected to the SU through a network link for implementing software control functions over the SU, wherein the SU comprises a plurality of functional components that are interconnected by generic buses, and wherein the components communicate-with one another using program data units (PDUs) that are formatted and transmitted according to a shared device protocol;

• wherein the components of the SU comprise the following components:
• at least one input/output module (IOM) for terminating network links;
• a cell memory (CM) for storing packets received from the network links until they are scheduled for transmission from the switch;
• and
• at least one cell processing module (CPM) directly connected to the memory for controlling the packet traffic flowing through the switch;
• wherein a plurality of IOMs are connected in series to each other such that a single given IOM is directly connected to components other than IOMs, and such that the rest of the IOMs must connect with the components other than IOMs through said single given IOM.

A packet switch comprising a switching unit (SU) for switching packets between network links, and a computing unit (CU) connected to the SU through a network link for implementing software control functions over the SU, wherein the SU comprises a plurality of functional components that are interconnected by generic buses, and wherein the components communicate with one another using program data units (PDUs) that are formatted and transmitted according to a shared device protocol;

• wherein the components of the SU comprise the following components:
• at least one input/output module (IOM) for terminating network links;
• a cell memory (CM) for storing packets received from the network links until they are scheduled for transmission from the switch;
• and
• at least one cell processing module (CPM) directly connected to the memory for controlling the packet traffic flowing through the switch;
• wherein a plurality of CPMs are connected in series to each other such that a single CPM is directly connected to components other than CPMs, and such that the rest of the CPMs must connect with the components other than CPMs through said single CPM.

A packet switch comprising a switching unit (SU) for switching packets between network links, and a computing unit (CU) connected to the SU through a network link for implementing software control functions over the SU, wherein the SU comprises a plurality of functional components that are interconnected by generic buses, and wherein the components communicate with one another using program data units (PDUs) that are formatted and transmitted according to a shared device protocol;

• wherein the components of the SU comprise the following components:
• at least one input/output module (IOM) for terminating network links;
• a cell memory (CM) for storing packets received from the network links until they are scheduled for transmission from the switch;
• and
• at least one cell processing module (CPM) directly connected to the memory for controlling the packet traffic flowing through the switch;
• wherein a plurality of IOMs are connected to components other than IOMs through a plurality of buses and a plurality of cross-connect modules (CCMs) that each contain a cross-connect switch, such that the ingress and egress flows through the switch can be divided into sub-flows that can each pass through one of a plurality of dynamically allocatable paths connecting the IOMs and the components other than IOMs.

A packet switch comprising a switching unit (SU) for switching packets between network links, and a computing unit (CU) connected to the SU through a network link for implementing software control functions over the SU, wherein the SU comprises a plurality of functional components that are interconnected by generic buses, and wherein the components communicate with one another using program data units (PDUs) that are formatted and transmitted according to a shared device protocol;

• wherein the components of the SU comprise the following components:
• at least one input/output module (IOM) for terminating network links;
• a cell memory (CM) for storing packets received from the network links until they are scheduled for transmission from the switch;
• and
• at least one cell processing module (CPM) directly connected to the memory for controlling the packet traffic flowing through the switch;
• wherein a plurality of CPMs are connected to components other than CPMs through a plurality of buses and a plurality of cross-connect modules (CCMS) that each contain a cross-connect switch, such that the ingress and egress flows through the switch can be divided into sub-flows that can each pass through one of a plurality of dynamically allocatable paths connecting the CPMs and the components other than CPMs.

A packet switch comprising a switching unit (SU) for switching packets between network links, and a computing unit (CU) connected to the SU through a network link for implementing software control functions over the SU, wherein the SU comprises a plurality of functional components that are interconnected by generic buses, and wherein the components communicate with one another using program data units (PDUs) that are formatted and transmitted according to a shared device protocol;

• wherein the components of the SU comprise the following components:
• at least one input/output module (IOM) for terminating network links;
• a cell memory (CM) for storing packets received from the network links until they are scheduled for transmission from the switch;
• and
• at least one cell processing module (CPM) directly connected to the memory for controlling the packet traffic flowing through the switch;
• wherein the CPM comprises the following:
• a Translation, Usage Parameter Control, and Buffer Management (TUB) component that is connected to a component external to the CPM, and which is used for performing ingress and egress address translations, for implementing policing functions, and for performing buffer management functions;
• an OAM Control Module (OCM) component that is connected to the TUB ASIC, and which is used for terminating and sourcing Operations, Administration and Maintenance (OAM) flows;
• an Available Bit Rate (ABR) processing subsystem (APS) component that is connected to the OCM component, and which is used for implementing rate based flow control;
• and
• a Queue Management and Scheduling Subsystem (QMS) component that is connected to the APS component, and which is used for maintaining packet queues and for scheduling packet transmissions from the switch.