Precharge control signal generator, and semiconductor memory device using the same

Abstract

A semiconductor memory device generates a precharge control signal asynchronous from a dock signal. The semiconductor memory device includes a memory cell array for storing data, and a precharge control signal generator for generating a precharge control signal in a test mode, by employing a predetermined control signal which does not influence access to the data stored in the memory cell array, even when maintained in a high or low level in the test mode. The precharge control signal generator receives the control signal, outputs a signal having an identical state to the control signal in the normal mode, and also outputs a signal fixed in a high or low level in the test mode. As a result, it is possible to generate the precharge control signal which does not require a delay time as long as a command hold time.

Dependencies are inferred from the claim text.