Asynchronous queuing circuit for DRAM external RAS accesses

A circuit for queuing asynchronous external memory requests for external RAS cycles of a DRAM, comprising:

• an address transition detection circuit that receives an external DRAM address change input signal a_in and that provides an address detection det_a_buf output signal and an address-stable addr_stable output signal;
• a RAS timer circuit that is provided with an input selection signal sel_xras that is active and that provides an output signal (xras_time1_b or xras1_b) that controls external RAS operation of the DRAM;
• an RS flip-flop (first latch) having an active output signal xr_rq that is set by the addr_stable signal going inactive when the xras_time1_b signal is inactive and that is reset when the xras_time1_b begins to be active;
• a RAS request queuing circuit, including:
• a D flip-flop circuit 118 (second latch) that has an output signal xque, that has a D input terminal for receiving the xras1_b signals and that has a clock terminal that receives an output signal from a 2-input AND gate (132,134) that receives a det_a_buf signal from the address transition detection circuit and that receives an inverted xque signal;
• and
• a queuing logic gate (NAND gate 138) that provides an active xque_start_b signal upon receipt of an active xque signal, an inactive addr_stable signal, and an inactive xras1_b signal, said active xque_start_b signal also resetting the D flip-flop 118.

A method of queuing asynchronous external memory requests for external RAS cycles of a DRAM having an SRAM-type interface, comprising:

• in response to any changes in address signals for the DRAM, generating a det_a_buf signal and generating an address stable signal addr_stable if the new address is stable;
• if there is no RAS cycle currently underway, then using the addr_stable signal to latch a first RAS request signal in a first latch;
• in response to the latched first RAS request signal, initiating a first RAS cycle;
• resetting the first latch when the first RAS cycle begins;
• if the first RAS cycle is currently underway, latching a subsequent, second RAS cycle request signal in a second latch using the det_a_buf signal;
• when the first RAS cycle is complete and, if the second latch contains a second RAS cycle request signal, initiating a second RAS cycle for the second RAS cycle request;
• and
• resetting the second latch when the second RAS cycle begins;
• then using the addr_stable signal to latch the first RAS request signal in the first latch.

A method of queuing asynchronous external memory requests for external RAS cycles of a DRAM having an SRAM-type interface, comprising:

• if there is no RAS cycle currently underway, then setting a first request latch in response to a first external RAS request signal;
• initiating a first RAS cycle in response to the first external RAS request signal;
• subsequently resetting the first request latch when the first RAS cycle corresponding to the first external RAS request signal begins;
• if there is a current RAS access cycle currently underway, setting a second in-progress latch in response to another external RAS request signal;
• when the current RAS access cycle is completed, if the second in-process latch is set, initiating a new RAS cycle for the second external RAS request signal and resetting both the first request latch and the second in-progress latches when a RAS cycle corresponding to the second external RAS request signal begins;
• whereby newly received RAS requests are queued the newly received access request signal arrives prior to completion of an access cycle already underway.