Synchronous memory devices with synchronized latency control circuits and methods of operating same

A method of operating a synchronous memory device, the method comprising:

• generating a second clock signal that lags a first clock signal by a first predetermined time;
• generating a third clock signal that leads the first clock signal by a second predetermined time;
• producing a transition in a read status signal in response to assertion of either of a read initiation signal indicative of initiation of a read operation or a read termination signal indicative of termination of the read operation;
• latching the read status signal responsive to the second clock signal to generate a synchronized read status signal;
• generating a latency control signal from the synchronized read status signal responsive to the third clock signal;
• generating an output control signal responsive to the latency control signal;
• and
• outputting data from an output buffer of the memory device responsive to the output control signal.

A latency control circuit of a synchronous semiconductor memory device for generating a latency control signal for determining the point of time, at which output data is generated, comprising:

• a read status signal generator circuit for enabling a read status signal in response to a read command signal and for disabling the read status signal in response to either an internal end signal or a stop command signal;
• a delay circuit for delaying the read status signal by one cycle of a first clock in response to the first clock that lags a system clock applied from the outside of the semiconductor memory device by a first predetermined phase difference;
• and
• a latency control signal generator circuit for sampling the delayed read status signal during a section where a second clock is at a first logic level and generating the latency control signal by delaying the sampled signal, wherein the second clock leads the system clock by a second predetermined phase difference.

A synchronous semiconductor memory device, comprising:

• a memory cell array;
• an internal clock generator for generating an internal clock in response to a system clock applied from the outside;
• a delay locked loop circuit for generating an output control clock in response to the system clock;
• a latency control circuit for generating a latency control signal for determining the point of time, at which output data is generated, in response to the output control clock;
• an output control circuit for generating an output control signal by delaying the latency control signal;
• and
• a data output buffer for outputting data read from the memory cell array as the output data to the outside in response to the output control signal,
• wherein the latency control circuit comprises:
• a read status signal generator circuit for generating a read status signal enabled in response to a read command signal applied from the outside and disabled in response to either an internal end signal or a stop command signal;
• a delay circuit for delaying the read status signal by one cycle of the internal clock in response to the internal clock;
• and
• a latency control signal generator circuit for sampling the delayed read status signal during the first logic level section of the output control clock and generating the latency control signal by delaying the sampled signal, in response to the output control clock.

A latency control method of a synchronous semiconductor memory device, comprising:

• generating an internal clock in response to a system clock applied from the outside;
• generating an output control clock in response to the system clock;
• generating a read status signal enabled in response to a read command signal applied from the outside and disabled in response to either an internal end signal or a stop command signal;
• delaying the read status signal by one cycle of the internal clock in response to the internal clock;
• and
• sampling the delayed read status signal during the first logic level section of the output control clock and generating the latency control signal by delaying the sampled signal in response to the output control signal.