Timing fuse method for delaying signals in a memory device
AssigneeMicron Technology, Inc.
InventorBrian M. Shirley
Life of this patent
Estimating the term…
Abstract
A fuse option for a dynamic random access memory (DRAM) is provided to selectively slow row address signals when redundant rows of memory cells have been selected for use. The fuse option is blown when a redundant row is used to replace a defective row as identified during manufacture of a DRAM. The fuse is coupled to delay circuitry which has a known delay. When the fuse is blown after detecting a defective row, the delay circuitry is coupled in series with selected portions of a row address strobe (RAS) chain of circuitry used to propagate row address selection signals to the proper rows. This provides extra time needed for row address compare and override circuitry, which is not in series with the delay circuitry.
Claims25
A method of delaying row address strobe signals in a semiconductor memory device, comprising:
- enabling a spare row of memory cells by setting a fuse in a fuse bank;
- and
- setting a signal fuse separate from the fuse bank to delay the row address strobe signals.
A method of delaying row address strobe signals in a semiconductor memory device, comprising:
- enabling a spare row of memory cells;
- and
- setting a slow down fuse, separate from enabling a spare row of memory cells, in a state to delay the row address strobe signals, wherein setting the slow down fuse occurs substantially simultaneously with enabling the spare row of memory cells.
A method of delaying row address strobe signals in a semiconductor memory device, comprising:
- probe testing the memory device at a wafer level;
- detecting a bad row of memory cells;
- setting a redundancy fuse to enable a spare row of memory cells for use in place of the bad row of memory cells;
- and
- setting a fast/slow fuse in a state to delay the row address strobe signals independent of enabling the spare row of memory cells in conjunction with enabling the spare row of memory cells for use in place of the bad row of memory cells.
A method of delaying row address strobe signals in a semiconductor memory device, comprising:
- providing redundant rows of memory cells;
- and
- coupling a fast/slow fuse by a conductive line to a control logic in the semiconductor memory device, the fast/slow fuse set in a condition to slow down a row address strobe chain, wherein the fast/slow fuse is set to another condition when no redundant rows are enabled.
A method of delaying row address strobe signals in a semiconductor memory device, comprising:
- enabling a spare row of memory cells by setting an antifuse in a bank of antifuses;
- and
- setting a signal antifuse separate from the bank of antifuses to delay the row address strobe signals after setting the antifuse in the bank of antifuses to enable the spare row of memory cells, wherein setting the signal antifuse is independent of enabling the spare row of memory cells.
A method of delaying row address strobe signals in a semiconductor memory device, comprising:
- testing the semiconductor memory device;
- detecting a defective row of memory cells;
- setting a redundancy fuse to enable a spare row of memory cells for use in place of the defective row of memory cells;
- and
- setting a fast/slow antifuse to delay the row address strobe signals in conjunction with enabling the spare row of memory cells for use in place of the defective row of memory cells, wherein setting the fast/slow antifuse is independent of enabling the spare row of memory cells.
A method of delaying row address strobe signals in a semiconductor memory device, comprising:
- testing the semiconductor memory device at a wafer level;
- determining if the semiconductor memory device has a defective row of memory cells;
- remapping a unique row address associated with the defective row of memory cells to a spare row of memory cells;
- and
- setting a fast/slow fuse to delay the row address strobe signals in conjunction with remapping the unique row address, wherein setting the fast/slow fuse is independent of remapping the unique row address.
A method of delaying row address strobe signals in a semiconductor memory device, comprising:
- testing the semiconductor memory device at a wafer level;
- determining if the semiconductor memory device has a defective row of memory cells;
- remapping a unique row address associated with the defective row of memory cells to a spare row of memory cells;
- and
- setting a fast/slow fuse to delay the row address strobe signals substantially simultaneously with remapping the unique row address, wherein setting the fast/slow fuse is independent of remapping the unique row address.
A method of delaying row address strobe signals in a semiconductor memory device, comprising:
- remapping a unique row address associated with a defective row of memory cells to a spare row of memory cells;
- and
- setting a fuse to delay the row address strobe signals in conjunction with remapping the unique row address, wherein setting the fuse is independent of remapping the unique row address.
Dependencies are inferred from the claim text.