Apparatus and method for refresh and data input device in SRAM having storage capacitor cell
AssigneeCoremagic, Inc.
InventorTae Hoon Kim
Life of this patent
Estimating the term…
Abstract
An apparatus for a refresh and a data input device in the SRAM having a storage capacitor cell comprises an internal clock generator for generating and outputting two internal clock signals having a certain time difference of each other, a refresh timer for generating and outputting an output signal to notify a refresh time, a refresh signal generator for generating a refresh signal in response to a faster signal of the two internal signals and the output signal from the refresh timer, a refresh counter for generating refresh addresses during the refresh and a column path controller for controlling the activation of a column path in response to a row active signal and the refresh signal.
Claims17
An apparatus for a refresh and a data input device in a static random access memory (SRAM) having a storage capacitor cell, comprising:
- an internal clock generating means for generating and outputting two internal clock signals having a certain time difference of each other;
- a refresh timer for generating and outputting an output signal to notify a refresh time;
- a refresh signal generating means for generating a refresh signal in response to a faster signal of the two internal signals and the output signal from the refresh timer;
- a refresh counter for generating refresh addresses during the refresh;
- and
- a column path control means for controlling the activation of a column path in response to a row active signal and the refresh signal.
A method for the a refresh and the a data input device in a static random access memory (SRAM) having a storage capacitor cell, comprising the steps of:
- a) generating two internal clocks having a certain time difference of each other;
- b) using a delayed signal of the two internal clocks as a strobe signal of an address;
- c) inputting an output signal from a refresh timer and generating a refresh signal in response to the faster signal of the two internal clocks;
- and
- d) selecting one of addresses, which are an external address and an internal address, for using a refresh signal.
A method for a refresh and the a data input device in a static random access memory (SRAM) having a storage capacitor cell, comprising the steps of:
- a) disabling an address when a refresh signal is enabled during a write operation;
- b) confirming a current state if it is the write operation when the refresh begins;
- c) generating a delay signal for notifying the refresh if it is the write operation after the step b);
- d) generating a write address and a latch signal of the data when the delay signal is generated;
- e) controlling an external input path of an address buffer using a write latch signal;
- f) latching an external address after the step e);
- and
- g) buffering the latched address after the refresh.
A method for a refresh and a data input device in a static random access memory (SRAM) having a storage capacitor cell, comprising the steps of:
- a) disabling an address when a refresh signal is enabled during a write operation;
- b) confirming a current state if it is the write operation when the refresh begins;
- c) generating a delay signal for notifying the refresh if it is the write operation after the step b);
- d) generating a write address and a latch signal of the data when the delay signal is generated;
- e) controlling a write driver using a write latch signal;
- f) latching an external address after the step e);
- and
- g) buffering the latched address after the refresh.
Dependencies are inferred from the claim text.