Semiconductor memory device including clock-independent sense amplifier

A semiconductor memory device comprising:

• a memory cell array having an array of a plurality of memory cells;
• a read control circuit which produces a precharging signal to precharge a bit line of the memory cell array;
• a row decoder which selects a word line of the memory cell array;
• a column decoder which selects the bit line of the memory cell array;
• a sense amplifier which amplifies data read from a memory cell selected by the row decoder and the column decoder to the bit line;
• and
• a sense amplifier control circuit which is responsive to the precharging signal to control the sense amplifier, in reading data from a memory cell, the sense amplifier control circuit enabling the sense amplifier and inhibiting entry of read data from the memory cell into the sense amplifier only for a fixed interval after a fixed time after the precharging signal has been negated and allowing entry of the read data into the sense amplifier while the sense amplifier is being disabled.