Memory device having read charge control, write charge control and floating or precharge circuits

A semiconductor memory device comprising:

• a plurality of memory cell array blocks having a plurality of memory cells connected between a plurality of word lines and a plurality of complementary bit line pairs, the blocks being selected in response to a plurality of block select signals;
• a predetermined number of complementary local data input/output line pairs of each of the plurality of memory cell array blocks transmitting data to the plurality of complementary bit line pairs of each of the plurality of memory cell array blocks;
• a circuit comprising a read charge control circuit activated by a read signal and an address and a write charge control circuit activated by a write signal and the same or a different address, the circuit being connected to each of the plurality of complementary bit line pairs;
• and
• a floating circuit being connected between each of the predetermined complementary local data input/output line pairs, the floating circuit establishing the predetermined complementary local data input/output line pairs of non-selected memory cell array blocks among the memory cell array blocks at floating states,
• wherein the write charge control circuit comprises:
• a fourth transistor having a first terminal controlled by the write signal and the same or different column address, and a second terminal and a third terminal connected to the bit line and the local data input/output line, respectively;
• and
• a fifth transistor having a first terminal controlled by the write signal and the same or different column address, and a second terminal and a third terminal connected to the complementary bit line and the complementary local data input/output line, respectively.

A semiconductor memory device comprising:

• a plurality of memory cell array blocks having a plurality of memory cells connected between a plurality of word lines and a plurality of complimentary bit line pairs, the blocks being selected in response to a plurality of block select signals;
• a predetermined number of complementary local data input/output line pairs of each of the plurality of memory cell array blocks transmitting data to the plurality of complementary bit line pairs of each of the plurality of memory cell array blocks;
• a circuit comprising a read charge control circuit activated by a read signal and an address and a write charge control circuit activated by a write signal and the same or a different address, the circuit being connected to each of the plurality of complementary bit line pairs;
• and
• a floating circuit being connected between each of the predetermined complementary local data input/output line pairs, the floating circuit establishing the predetermined complementary local data input/output line pairs of non-selected memory cell array blocks among the memory cell array blocks at floating states,
• wherein the floating circuit comprises:
• a sixth transistor having a first terminal controlled in response to the block select signal, and a second terminal and a third terminal connected to the local data input/output line and the complementary local data input/output line, respectively.

A semiconductor memory device comprising:

• a plurality of memory cell array blocks having a plurality of memory cells connected between a plurality of word lines and a plurality of complementary bit line pairs, and being selected in response to a plurality of block select signals;
• a predetermined number of complementary local data input/output line pairs of each of the plurality of memory cell array blocks transmitting data to the plurality of complementary bit line pairs of each of the plurality of memory cell array blocks;
• a circuit comprising a read charge control circuit activated by the block select signal, a read signal and an address and a write charge control circuit activated by a write signal and the same or a different address, the circuit being connected to each of the plurality of complementary bit line pairs;
• and
• a pre-charge circuit being connected between each of the predetermined complementary local data input/output line pairs of each of the plurality of memory cell array block, and pre-charging each of the complementary local data input/output line pairs,
• wherein the read charge control circuit comprises:
• a first transistor having a first terminal connected to a bit line, and a second terminal and a third terminal connected to a complementary local data input/output line and a first node, respectively;
• a second transistor having a first terminal connected to a complementary bit line, and a second terminal and a third terminal connected to a local data input/output line and the first node, respectively;
• a third transistor having a first terminal controlled by the read signal and the column address and a second terminal and a third terminal connected to the first node and a second node, respectively;
• and
• a fourth transistor having a first terminal in response to the block select signal and a second terminal and a third terminal connected to the second node and a ground voltage, respectively.

A semiconductor memory device comprising:

• a plurality of memory cell array blocks having a plurality of memory cells connected between a plurality of word lines and a plurality of complementary bit line pairs, and being selected in response to a plurality of block select signals;
• a predetermined number of complementary local data input/output line pairs of each of the plurality of memory cell array blocks transmitting data to the plurality of complementary bit line pairs of each of the plurality of memory cell array blocks;
• a circuit comprising a read charge control circuit activated by the block select signal, a read signal and an address and a write charge control circuit activated by a write signal and the same or a different address, the circuit being connected to each of the plurality of complementary bit line pairs;
• and
• a pre-charge circuit being connected between each of the predetermined complementary local data input/output line pairs of each of the plurality of memory cell array block, and pre-charging each of the complementary local data input/output line pairs,
• wherein the write charge control circuit comprises:
• a fifth transistor having a first terminal controlled by the write signal and the same or different column address, and a second terminal and a third terminal connected to the bit line and the local data input/output line, respectively;
• and
• a sixth transistor having a first terminal controlled by the write signal and the same or different column address, and a second terminal and a third terminal connected to the complementary bit line and the complementary local data input/output line, respectively.