Self-healing MRAM
AssigneeHewlett-Packard Development Company, L.P.
InventorsKenneth J. Eldredge, Kenneth K. Smith
Life of this patent
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Abstract
An MRAM device includes an array of memory cells. A plurality of traces cross the memory cells. An address decoder coupled to the plurality of traces decodes an address and selects a corresponding subset of the traces. A sparing circuit coupled to the address decoder receives a logical address and outputs a physical address to the address decoder based on memory cell defect information.
Claims19
An MRAM device comprising:
- an array of memory cells;
- a plurality of rows of traces crossing the memory cells;
- a plurality of columns of traces crossing the memory cells;
- a row decoder coupled to the plurality of rows of traces for decoding a row address and selecting at least one of the rows of traces;
- a sparing circuit coupled to the row decoder for receiving a logical address and outputting a physical address to the row decoder and
- wherein the sparing circuit includes a plurality of comparators for comparing the received logical address to comparison values, the comparison values based on memory cell defect information, each of the comparators configured to output an offset value based on the comparison, and wherein the physical address is generated based on a sum of the offset values and the logical address.
A method of selecting at least one memory cell in a block-oriented memory device for read/write operations, the method comprising:
- identifying defective memory cells in the memory device;
- receiving a logical address;
- comparing the received logical address to a plurality of comparison values, the comparison values based on the identified defective memory cells;
- generating an offset value for each of the comparisons, thereby generating a plurality of offset values;
- generating a physical address by adding the plurality of offset values and the received logical address;
- and
- selecting at least one memory cell in the memory device for a read/write operation based on the generated physical address.
A sparing circuit for an MRAM device comprising:
- a plurality of comparators configured to receive a logical address and compare the received logical address to comparison values, the comparison values based on locations of memory cell defects in the MRAM device, each of the comparators configured to output an offset value based on the comparison;
- and
- at least one summing circuit configured to receive the offset values and the logical address, the summing circuit configured to add the received offset values to the received logical address, thereby generating a physical address to be provided to at least one address decode circuit of the MRAM device.
Dependencies are inferred from the claim text.